VHDL-based design and design methodology for reusable high performance direct digital requency synthesizers

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Authors: Ireneusz Janiszewski FH Darmstadt, Fachbereich Elektrotechnik, Schöfferstr. 3, D-64295 Darmstadt
Bernhard Hoppe FH Darmstadt, Fachbereich Elektrotechnik, Schöfferstr. 3, D-64295 Darmstadt
Hermann Meuth FH Darmstadt, Fachbereich Elektrotechnik, Schöfferstr. 3, D-64295 Darmstadt
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· Proceeding
DAC '01 Proceedings of the 38th annual Design Automation Conference
Pages 573-578
ACM New York, NY, USA ©2001
table of contents ISBN:1-58113-297-2 doi>10.1145/378239.379026
VHDL-based design and design methodology for reusable high performance direct digital requency synthesizers Published by ACM 2001 Article
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