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Integrating scheduling and physical design into a coherent compilation cycle for reconfigurable computing architectures
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Authors:
Kia Bazargan
ECE Department, University of Minnesota, Minneapolis, MN
Seda Ogrenci
CS Department, UCLA, Los Angeles, CA
Majid Sarrafzadeh
CS Department, UCLA, Los Angeles, CA
Published in:
· Proceeding
DAC '01
Proceedings of the 38th annual Design Automation Conference
Pages 635-640
ACM
New York, NY
, USA
©2001
table of contents
ISBN:1-58113-297-2
doi>
10.1145/378239.379038
2001 Article
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· Downloads (12 Months): 11
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· Citation Count: 5
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design
electronics
experimentation
gate arrays
hardware description languages
languages
measurement
performance
scheduling
sequencing and scheduling
theory
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