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Computational power of pipelined memory hierarchies
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Authors:
Gianfranco Bilardi
Dip. Elettronica e Informatica, Università di Padova, Padova, Italy
Kattamuri Ekanadham
T.J. Watson Research Center, IBM, Yorktown Heights, NY
Pratap Pattnaik
T.J. Watson Research Center, IBM, Yorktown Heights, NY
Published in:
· Proceeding
SPAA '01
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Pages 144-152
ACM
New York, NY
, USA
©2001
table of contents
ISBN:1-58113-409-6
doi>
10.1145/378580.378615
2001 Article
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algorithms
measurement
memory technologies
parallelism and concurrency
performance
pipeline processors
theory
verification
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