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Functional verification of MOS circuits
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Author:
D. Weise
Stanford University, Computer Systems Laboratory, Center for Integrated Systems 207, Stanford, California
Published in:
· Proceeding
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Pages 265-270
ACM
New York, NY
, USA
©1987
table of contents
ISBN:0-8186-0781-5
doi>
10.1145/37888.37928
1987 Article
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· Citation Count: 4
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design
memory technologies
verification
verification
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