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Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
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Authors:
A. Keshavarzi
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
S. Ma
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
S. Narendra
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
B. Bloechel
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
K. Mistry
Portland Technology Development, Intel Corporation, Hillsboro, OR
T. Ghani
Portland Technology Development, Intel Corporation, Hillsboro, OR
S. Borkar
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
V. De
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
2001 Article
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Published in:
· Proceeding
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Pages 207-212
ACM
New York, NY
, USA
©2001
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ISBN:1-58113-371-5
doi>
10.1145/383082.383135
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design
experimentation
memory design
microprocessors and microcomputers
performance
signal processing
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