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FPGA interconnect planning
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Authors:
Amit Singh
University of California, Santa Barbara, Santa Barbara, CA
Malgorzata Marek-Sadowska
University of California, Santa Barbara, Santa Barbara, CA
Published in:
· Proceeding
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Pages 23 - 30
ACM
New York, NY
, USA
©2002
table of contents
ISBN:1-58113-481-9
doi>
10.1145/505348.505353
2002 Article
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experimentation
gate arrays
performance
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