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Global interconnect trade-off for technology over memory modules to application level: case study
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Authors:
A. Papanikolaou
IMEC, Kapeldreef, Leuven, Belgium
M. Miranda
IMEC, Kapeldreef, Leuven, Belgium
F. Catthoor
IMEC, Kapeldreef, Leuven, Belgium and Katholieke Universiteit Leuven, Belgium
H. Corporaal
IMEC, Kapeldreef, Leuven, Belgium and Technical University of Eindhoven, The Netherlands
H. De Man
IMEC, Kapeldreef, Leuven, Belgium and Katholieke Universiteit Leuven, Belgium
D. De Roest
IMEC, Kapeldreef, Leuven, Belgium
M. Stucchi
IMEC, Kapeldreef, Leuven, Belgium
Karen Maex
IMEC, Kapeldreef, Leuven, Belgium and Katholieke Universiteit Leuven, Belgium
2003 Article
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Published in:
· Proceeding
SLIP '03
Proceedings of the 2003 international workshop on System-level interconnect prediction
Pages 125 - 132
ACM
New York, NY
, USA
©2003
table of contents
ISBN:1-58113-627-7
doi>
10.1145/639929.639954
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Tags:
design
interconnect wire processing
interconnections
intra/inter-memory interconnect
pareto-optimal energy/delay interconnect exploration
static memory
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