A hierarchical three-way interconnect architecture for hexagonal processors

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Authors: Feng Zhou University of California, San Diego, La Jolla, CA
Esther Y. Cheng University of California, San Diego, La Jolla, CA
Bo Yao University of California, San Diego, La Jolla, CA
Chung-Kuan Cheng University of California, San Diego, La Jolla, CA
Ronald Graham University of California, San Diego, La Jolla, CA
A hierarchical three-way interconnect architecture for hexagonal processors Published by ACM 2003 Article
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· Proceeding
SLIP '03 Proceedings of the 2003 international workshop on System-level interconnect prediction
Pages 133 - 139
ACM New York, NY, USA ©2003
table of contents ISBN:1-58113-627-7 doi>10.1145/639929.639955

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