Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time

doi:10.1145/640000.640036

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Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time

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Authors:	Jeng-Liang Tsai	University of Wisconsin-Madison, Madison, WI
	Tsung-Hao Chen	University of Wisconsin-Madison, Madison, WI
	Charlie Chung-Ping Chen	National Taiwan University, Taipei, Taiwan

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	· Proceeding
	ISPD '03 Proceedings of the 2003 international symposium on Physical design
	ACM New York, NY, USA ©2003 table of contents ISBN:1-58113-650-1 doi>10.1145/640000.640036

	2003 Article
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· Downloads (6 Weeks): 2 · Downloads (12 Months): 19 · Citation Count: 5

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Tags: ε-optimal algorithms clock tree incremental refinement performance analysis and design aids pseudo-polynomial wire-sizing zero-skew

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