Partitioned instruction cache architecture for energy efficiency

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Authors: Soontae Kim The Pennsylvania State University, University Park, PA
N. Vijaykrishnan The Pennsylvania State University, University Park, PA
Mahmut Kandemir The Pennsylvania State University, University Park, PA
Anand Sivasubramaniam The Pennsylvania State University, University Park, PA
Mary Jane Irwin The Pennsylvania State University, University Park, PA
Partitioned instruction cache architecture for energy efficiency Published by ACM 2003 Article
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ACM Transactions on Embedded Computing Systems (TECS) TECS Homepage archive
Volume 2 Issue 2, May 2003
Pages 163 - 185
ACM New York, NY, USA
table of contents doi>10.1145/643470.643473

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