The use of inverse layout trees for hierarchical design rule checking

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Authors: N. Hedenstierna Chalmers University of Technology, School of Electrical and Computer Engineering, Departmem of Solid-State Electronics, S-4 12 96 Goteborg, Sweden
K. O. Jeppson Chalmers University of Technology, School of Electrical and Computer Engineering, Departmem of Solid-State Electronics, S-4 12 96 Goteborg, Sweden
Published in:
· Proceeding
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Pages 508-512
ACM New York, NY, USA ©1989
table of contents ISBN:0-89791-310-8 doi>10.1145/74382.74467
The use of inverse layout trees for hierarchical design rule checking Published by ACM 1989 Article
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