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Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture
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Authors:
Manuel E. Acacio
Universidad de Murcia, Spain
José González
Intel Barcelona Research Center, Intel Labs, Barcelona
José M. García
Universidad de Murcia, Spain
José Duato
Universidad Politécnica de Valencia, Spain
2002 Article
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· Proceeding
Supercomputing '02
Proceedings of the 2002 ACM/IEEE conference on Supercomputing
Pages 1-12
IEEE Computer Society Press
Los Alamitos, CA
, USA
©2002
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cache memories
design
multiple-instruction-stream, multiple-data-stream processors
performance
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