A novel architecture for power maskable arithmetic units

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Authors: L. Benini Università di Bologna, Bologna, Italy
A. Macii Politecnico di Torino, Torino, Italy
E. Macii Politecnico di Torino, Torino, Italy
E. Omerbegovic BullDAST s.r.l., Torino, Italy
M. Poncino Università di Verona, Verona, Italy
F. Pro BullDAST s.r.l., Torino, Italy
A novel architecture for power maskable arithmetic units Published by ACM 2003 Article
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GLSVLSI '03 Proceedings of the 13th ACM Great Lakes symposium on VLSI
Pages 136 - 140
ACM New York, NY, USA ©2003
table of contents ISBN:1-58113-677-3 doi>10.1145/764808.764845

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