40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications

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Authors: Michael I. Fuller University of Virginia, Charlottesville, VA
James P. Mabry University of Virginia, Charlottesville, VA
John A. Hossack University of Virginia, Charlottesville, VA
Travis N. Blalock University of Virginia, Charlottesville, VA
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications Published by ACM 2003 Article
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GLSVLSI '03 Proceedings of the 13th ACM Great Lakes symposium on VLSI
Pages 182 - 185
ACM New York, NY, USA ©2003
table of contents ISBN:1-58113-677-3 doi>10.1145/764808.764855

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