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Low-power design methodology for an on-chip bus with adaptive bandwidth capability
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Authors:
Rizwan Bashirullah
North Carolina State University, Raleigh, NC
Wentai Liu
University of California, Santa Cruz, CA
Ralph K. Cavin
Semiconductor Research Corporation, Research Triangle Park, NC
Published in:
· Proceeding
DAC '03
Proceedings of the 40th annual Design Automation Conference
Pages 628-633
ACM
New York, NY
, USA
©2003
table of contents
ISBN:1-58113-688-9
doi>
10.1145/775832.775990
2003 Article
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· Citation Count: 6
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Tags:
bus
current-mode
delay
design
low-power
on-chip interconnect
performance
point-to-point
topology
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