On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices

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Authors: D. Goren IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
M. Zelikson IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
R. Gordin IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
I. A. Wagner IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
A. Barger IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
A. Amir IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
B. Livshitz IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
A. Sherman IBM Haifa Research and Development Labs, MATAM, Haifa, Israel
Y. Tretiakov IBM Design Automation Dept. Burlington, US
R. Groves IBM SiGe Model Development, East Fishkill, US
J. Park IBM SiGe Model Development, East Fishkill, US
D. Jordan IBM Design Automation Dept. Burlington, US
S. Strang IBM Design Automation Dept. Burlington, US
R. Singh IBM Design Automation Dept. Burlington, US
C. Dickey IBM Design Automation Dept. Burlington, US
D. Harame IBM Design Automation Dept. Burlington, US
On-chip interconnect-aware design and modeling methodology, based on high bandwidth transmission line devices Published by ACM 2003 Article
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· Proceeding
DAC '03 Proceedings of the 40th annual Design Automation Conference
Pages 724-727
ACM New York, NY, USA ©2003
table of contents ISBN:1-58113-688-9 doi>10.1145/775832.776017

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