SIGN IN
SIGN UP
Hybrid hierarchical timing closure methodology for a high performance and low power DSP
Full Text:
PDF
Buy this Article
Authors:
Kaijian Shi
Professional Services, Synopsys Inc., Dallas, TX
Graig Godwin
Texas Instruments, Inc., Dallas, TX
Published in:
· Proceeding
DAC '03
Proceedings of the 40th annual Design Automation Conference
ACM
New York, NY
, USA
©2003
table of contents
ISBN:1-58113-688-9
doi>
10.1145/775832.776046
2003 Article
Bibliometrics
· Downloads (6 Weeks): 1
· Downloads (12 Months): 8
· Citation Count: 1
Tools and Resources
Buy this Article
Request Permissions
TOC Service:
Email
RSS
Save to Binder
Export Formats:
BibTeX
EndNote
ACM Ref
Upcoming Conference:
DAC '12
Share:
|
Tags:
chip integration
design
dsp
methodology
placement optimization
timing closure
Feedback
|
Switch to
single page view
(no tabs)
**Javascript is not enabled and is required for the "tabbed view" or switch to the
single page view
**
Powered by
The ACM Guide to Computing Literature
All Tags
Export Formats
Save to Binder