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Performance of memory configurations for parallel-pipelined computers
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Author:
Fayé A. Briggs
Published in:
· Proceeding
ISCA '78 Proceedings of the 5th annual symposium on Computer architecture
Pages 202-209
ACM
New York, NY
, USA
©1978
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doi>
10.1145/800094.803049
1978 Article
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design
performance
pipeline processors
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