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Exploiting program hotspots and code sequentiality for instruction cache leakage management
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Authors:
J. S. Hu
The Pennsylvania State University, University Park, PA
A. Nadgir
The Pennsylvania State University, University Park, PA
N. Vijaykrishnan
The Pennsylvania State University, University Park, PA
M. J. Irwin
The Pennsylvania State University, University Park, PA
M. Kandemir
The Pennsylvania State University, University Park, PA
2003 Article
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· Citation Count: 13
Published in:
· Proceeding
ISLPED '03
Proceedings of the 2003 international symposium on Low power electronics and design
Pages 402-407
ACM
New York, NY
, USA
©2003
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ISBN:1-58113-682-X
doi>
10.1145/871506.871606
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Tags:
cache design
cache memories
design
leakage power
measurement
performance
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