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Energy characterization of a tiled architecture processor with on-chip networks
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Authors:
Jason Sungtae Kim
MIT Laboratory for Computer Science
Michael Bedford Taylor
MIT Laboratory for Computer Science
Jason Miller
MIT Laboratory for Computer Science
David Wentzlaff
MIT Laboratory for Computer Science
2003 Article
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· Downloads (12 Months): 36
· Downloads (cumulative): 489
· Citation Count: 25
Published in:
· Proceeding
ISLPED '03
Proceedings of the 2003 international symposium on Low power electronics and design
Pages 424-427
ACM
New York, NY
, USA
©2003
table of contents
ISBN:1-58113-682-X
doi>
10.1145/871506.871610
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Tags:
design
distributed architectures
measurement
performance
power
raw microprocessor
scalar operand network
tile
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