A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate

doi:10.1145/871506.871614

A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate

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Authors:	Jonghae Kim	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Jean-Olivier Plouchart	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Noah Zamdmer	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Melanie Sherony	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Yue Tan	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Meeyoung Yoon	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Robert Trzcinski	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Mohamed Talbi	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	John Safran	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Asit Ray	IBM Semiconductor Research and Development Center, Hopewell Junction, NY
	Lawrence Wagner	IBM Semiconductor Research and Development Center, Hopewell Junction, NY

	2003 Article
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	· Proceeding
	ISLPED '03 Proceedings of the 2003 international symposium on Low power electronics and design
	Pages 434-439 ACM New York, NY, USA ©2003 table of contents ISBN:1-58113-682-X doi>10.1145/871506.871614

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Tags: advanced technologies design high resistivity substrate low power phase noisefom rf design soi cmos vco

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