A graphical system for hierarchical specifications and checkups of VLSI circuits

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Authors: B. Becker Universität des Saarlandes, D-6600 Saarbrücken, FRG
Th. Burch Universität des Saarlandes, D-6600 Saarbrücken, FRG
G. Hotz Universität des Saarlandes, D-6600 Saarbrücken, FRG
D. Kiel Universität des Saarlandes, D-6600 Saarbrücken, FRG
R. Kolla Universität des Saarlandes, D-6600 Saarbrücken, FRG
P. Molitor Universität des Saarlandes, D-6600 Saarbrücken, FRG
H. G. Osthof Universität des Saarlandes, D-6600 Saarbrücken, FRG
G. Pitsch Universität des Saarlandes, D-6600 Saarbrücken, FRG
U. Sparmann Universität des Saarlandes, D-6600 Saarbrücken, FRG
A graphical system for hierarchical specifications and checkups of VLSI circuits 1990 Article
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Published in:
· Proceeding
EURO-DAC '90 Proceedings of the conference on European design automation
Pages 174-179
IEEE Computer Society Press Los Alamitos, CA, USA ©1990
table of contents ISBN:0-8186-2024-2

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