Hierarchical layout verification for submicron designs

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Author: W. Meier Siemens AG, Corporate Research and Development, D-8000 Munich 83
Published in:
· Proceeding
EURO-DAC '90 Proceedings of the conference on European design automation
Pages 382-386
IEEE Computer Society Press Los Alamitos, CA, USA ©1990
table of contents ISBN:0-8186-2024-2
Hierarchical layout verification for submicron designs 1990 Article
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