Task-level timing models for guaranteed performance in multiprocessor networks-on-chip

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Authors: P. Poplavko Eindhoven University of Technology, Eindhoven, The Netherlands and Philips Research Laboratories Eindhoven, Eindhoven, The Netherlands
T. Basten Eindhoven University of Technology, Eindhoven, The Netherlands
M. Bekooij Philips Research Laboratories Eindhoven, Eindhoven, The Netherlands
J. van Meerbergen Eindhoven University of Technology, Eindhoven, The Netherlands and Philips Research Laboratories Eindhoven, Eindhoven, The Netherlands
B. Mesman Eindhoven University of Technology, Eindhoven, The Netherlands and Philips Research Laboratories Eindhoven, Eindhoven, The Netherlands
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip Published by ACM 2003 Article
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CASES '03 Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Pages 63-72
ACM New York, NY, USA ©2003
table of contents ISBN:1-58113-676-5 doi>10.1145/951710.951721

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