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Reducing Design Complexity of the Load/Store Queue
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Authors:
Il Park
School of Electrical and Computer Engineering, Purdue University
Chong Liang Ooi
School of Electrical and Computer Engineering, Purdue University
T. N. Vijaykumar
School of Electrical and Computer Engineering, Purdue University
Published in:
· Proceeding
MICRO 36
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Page 411
IEEE Computer Society
Washington, DC
, USA
©2003
table of contents
ISBN:0-7695-2043-X
2003 Article
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design
input/output circuits
memory technologies
microprocessors and microcomputers
performance
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