Design and Implementation of High-Performance Memory Systems for Future Packet Buffers

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Authors: Jorge García Polytechnic University of Catalonia - Computer Architecture Dept.
Jesús Corbal Polytechnic University of Catalonia - Computer Architecture Dept.
Llorenç Cerdà Polytechnic University of Catalonia - Computer Architecture Dept.
Mateo Valero Polytechnic University of Catalonia - Computer Architecture Dept.
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers 2003 Article
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MICRO 36 Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Page 373
IEEE Computer Society Washington, DC, USA ©2003
table of contents ISBN:0-7695-2043-X

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