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Formal hardware specification languages for protocol compliance verification
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Authors:
Annette Bunker
University of Utah, Salt Lake City, UT
Ganesh Gopalakrishnan
University of Utah, Salt Lake City, UT
Sally A. Mckee
Cornell University, Ithaca, NY
Published in:
· Journal
ACM Transactions on Design Automation of Electronic Systems (TODAES)
TODAES Homepage
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Volume 9 Issue 1, January 2004
Pages 1 - 32
ACM
New York, NY
, USA
table of contents
doi>
10.1145/966137.966138
2004 Article
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· Citation Count: 4
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Tags:
data types and structures
e
esterel
hardware monitors
heterogeneous hardware logic
hierarchical annotated action diagrams
interfaces
java
languages
lava
live sequence charts
message sequence charts
objective vhdl
openvera
property specification language
protocol verification
specc
specification and description language
statecharts
systemc
systemverilog
the unified modeling language
timing diagrams
verification
verification
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