Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger

Authors: C. Hinkelbein University of Mannheim, Germany
A. Khomich University of Mannheim, Germany
A. Kugel University of Mannheim, Germany
R. Männer University of Mannheim, Germany
M. Müller University of Mannheim, Germany
Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger Published by ACM 2004 Article
Bibliometrics Data  Bibliometrics
· Downloads (6 Weeks): n/a
· Downloads (12 Months): n/a
· Downloads (cumulative): n/a
· Citation Count: 0

Published in:
Cover Image
 
· Proceeding
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Pages 247-247
ACM New York, NY, USA ©2004
table of contents ISBN:1-58113-829-6 doi>10.1145/968280.968321

Tools and Resources

Share:

|
feedback Feedback | Switch to single page view (no tabs)

Powered by The ACM Guide to Computing Literature


The ACM Digital Library is published by the Association for Computing Machinery. Copyright © 2013 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player
The ACM Guide to Computing Literature
All Tags
Export Formats
 
 
Save to Binder