Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier

Authors: Jae-Jin Lee Chungbuk National University, Cheongju Chungbuk, Korea
Gi-Yong Song Chungbuk National University, Cheongju Chungbuk, Korea
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· Proceeding
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Pages 249-249
ACM New York, NY, USA ©2004
table of contents ISBN:1-58113-829-6 doi>10.1145/968280.968328
Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier Published by ACM 2004 Article
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