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Power-aware clock tree planning
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Authors:
Monica Donno
BullDAST s.r.l., Torino, Italy
Enrico Macii
Politecnico di Torino, Torino, Italy
Luca Mazzoni
Accent s.r.l., Vimercate, Italy
Published in:
· Proceeding
ISPD '04
Proceedings of the 2004 international symposium on Physical design
Pages 138-147
ACM
New York, NY
, USA
©2004
table of contents
ISBN:1-58113-817-2
doi>
10.1145/981066.981097
2004 Article
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· Citation Count: 10
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Tags:
clock tree synthesis and routing
design
digital design
integrated circuits
logic design
low-power design
physical design and optimization
register-transfer-level implementation
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