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On-chip delay measurement for silicon debug
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Authors:
Ramyanshu Datta
The University of Texas at Austin, Austin, TX
Antony Sebastine
The University of Texas at Austin, Austin, TX
Ashwin Raghunathan
The University of Texas at Austin, Austin, TX
Jacob A. Abraham
The University of Texas at Austin, Austin, TX
2004 Article
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· Citation Count: 7
Published in:
· Proceeding
GLSVLSI '04
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Pages 145-148
ACM
New York, NY
, USA
©2004
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ISBN:1-58113-853-9
doi>
10.1145/988952.988988
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Tags:
delay fault testing
design for testability
measurement
performance
reliability
reliability, testing, and fault-tolerance
silicon debug
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