An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance

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Authors: Hasan Arslan University of Illinois-Chicago, Chicago, IL
Shantanu Dutt University of Illinois-Chicago, Chicago, IL
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· Proceeding
GLSVLSI '04 Proceedings of the 14th ACM Great Lakes symposium on VLSI
Pages 208-213
ACM New York, NY, USA ©2004
table of contents ISBN:1-58113-853-9 doi>10.1145/988952.989003
An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance Published by ACM 2004 Article
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