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Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages
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Authors:
Chung-Seok (Andy) Seo
Georgia Institute of Technology, Atlanta, GA
Abhijit Chatterjee
Georgia Institute of Technology, Atlanta, GA
Sang-Yeon Cho
Duke University, Durham, NC
Nan M. Jokerst
Duke University, Durham, NC
2004 Article
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Published in:
· Proceeding
GLSVLSI '04
Proceedings of the 14th ACM Great Lakes symposium on VLSI
ACM
New York, NY
, USA
©2004
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ISBN:1-58113-853-9
doi>
10.1145/988952.989023
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Tags:
algorithms
asymmetric structure
clock distribution
clock routing
h-tree
interconnections
optical clock distribution
optical waveguide loss modeling
optimization
optoelectronic system-on-a-package
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