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 Avi Mendelson

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Average citations per article7.97
Citation Count271
Publication count34
Publication years1994-2012
Available for download18
Average downloads per article592.56
Downloads (cumulative)10,666
Downloads (12 Months)183
Downloads (6 Weeks)29
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34 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
January 2012 ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers: Volume 8 Issue 4, January 2012
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 4,   Downloads (12 Months): 22,   Downloads (Overall): 907

Full text available: PDFPDF
GPGPUs are optimized for graphics, for that reason the hardware is optimized for massively data parallel applications characterized by predictable memory access patterns and little control flow. For such applications' e.g., matrix multiplication, GPGPU based system can achieve very high performance. However, many general purpose data parallel applications are characterized ...
Keywords: GPGPU, parallel machines, scheduling algorithm

2
January 2010 IEEE Transactions on Dependable and Secure Computing: Volume 7 Issue 1, January 2010
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 4

Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft errors still occur infrequently, they are rapidly becoming a major impediment to processor reliability. This is due primarily to processor ...
Keywords: Transient faults, fault tolerance, Double Execution, Micro-architecture, Transient faults, soft errors, superscalar, fault tolerance, microarchitecture, double execution., Fault tolerance, Soft Errors, Superscalar, microarchitecture, superscalar, double execution., soft errors

3 published by ACM
December 2009 MICRO 42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: ACM
Bibliometrics:
Citation Count: 10
Downloads (6 Weeks): 1,   Downloads (12 Months): 6,   Downloads (Overall): 551

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Power and thermal are major constraints for delivering compute performance in high-end CPU and are expected to be so in the future. CMP is becoming important by delivering more compute performance within the power constraints. Dynamic Voltage and Frequency Scaling (DVFS) has been studied in past work as a mean ...
Keywords: DVFS, chip multi processor, clock domains, power management, voltage domain

4 published by ACM
July 2009 ACM Transactions on Architecture and Code Optimization (TACO): Volume 6 Issue 2, June 2009
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 4,   Downloads (12 Months): 19,   Downloads (Overall): 541

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Multithreading is widely used to increase processor throughput. As the number of shared resources increase, managing them while guaranteeing predicted performance becomes a major problem. Attempts have been made in previous work to ease this via different fairness mechanisms. In this article, we present a new approach to control the ...
Keywords: Service level agreement, fairness, performance, power, throughput

5 published by ACM
June 2009 PLDI '09: Proceedings of the 30th ACM SIGPLAN Conference on Programming Language Design and Implementation
Publisher: ACM
Bibliometrics:
Citation Count: 34
Downloads (6 Weeks): 2,   Downloads (12 Months): 19,   Downloads (Overall): 2,132

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The client computing platform is moving towards a heterogeneous architecture consisting of a combination of cores focused on scalar performance, and a set of throughput-oriented cores. The throughput oriented cores (e.g. a GPU) may be connected over both coherent and non-coherent interconnects, and have different ISAs. This paper describes a ...
Keywords: heterogeneous platforms, programming model
Also published in:
May 2009  ACM SIGPLAN Notices - PLDI '09: Volume 44 Issue 6, June 2009

6
January 2009 IEEE Computer Architecture Letters: Volume 8 Issue 1, January 2009
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 20

We study the tradeoffs between Many-Core machines like Intel’s Larrabee and Many-Thread machines like Nvidia and AMD GPGPUs. We define a unified model describing a superposition of the two architectures, and use it to identify operation zones for which each machine is more suitable. Moreover, we identify an intermediate zone ...
Keywords: Multi-core/single-chip multiprocessors,Parallel Architectures, Processor Architectures, Computer Systems, Processor Architectures, Parallel Architectures, Processor Architectures, Multi-core/single-chip multiprocessors, Computer Systems

7 published by ACM
March 2008 DATE '08: Proceedings of the conference on Design, automation and test in Europe
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 2,   Downloads (Overall): 67

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Embedded Systems are pervasively appearing in virtually all walks of life - communication, computing, e-/m-commerce, leisure, medical, WSN, transportation, biometrics. The utility of these embedded systems and services is based, in large part, in our depending on their sustained functionality in spite of the encountered operational or malicious disruptions. As ...

8
September 2007 ICPP '07: Proceedings of the 2007 International Conference on Parallel Processing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Code generation for a multithreaded register sharing architecture is inherently complex and involves some issues absent in conventional code compilation. To approach the problem, we define a consistency contract between the program and the hardware and require the compiler to preserve the contract during code transformations. To apply the contract ...
Keywords: Fine grain parallelization, register sharing, multithreading, explicitly parallel code, register allocation, optimizations.

9 published by ACM
September 2007 ACM Transactions on Architecture and Code Optimization (TACO): Volume 4 Issue 3, September 2007
Publisher: ACM
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 4,   Downloads (12 Months): 19,   Downloads (Overall): 670

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The need to reduce power and complexity will increase the interest in Switch On Event multithreading (coarse-grained multithreading). Switch On Event multithreading is a low-power and low-complexity mechanism to improve processor throughput by switching threads on execution stalls. Fairness may, however, become a problem in a multithreaded processor. Unless fairness ...
Keywords: SOE, Switch on Event multithreading, coarse-grained multithreading, fairness, multithreading, performance, throughput, weighted speedup

10 published by ACM
June 2007 ICS '07: Proceedings of the 21st annual international conference on Supercomputing
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 11,   Downloads (Overall): 532

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Power thermal and process limitations encourage modern processors to integrate few cores on the same die in order to maintain overall performance growth, expected by the industry. While two years ago, most processors where single core configuration, the majority of the current processors contain dual or quad cores and the ...

11 published by ACM
March 2007 PPoPP '07: Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 10,   Downloads (Overall): 436

Full text available: PDFPDF
We investigate extremely fine-grain multithreading as a means for improving energy efficiency of single-task program execution.Our work is based on low-overhead threads executing an explicitly parallel program in a register-sharing context. The thread-based parallelism takes the place of instruction-level parallelism, allowing us to use simple and more energy-efficient in-order pipelines ...
Keywords: energy efficiency, fine grain parallelization, register sharing

12 published by ACM
February 2007 ACM Transactions on Computer Systems (TOCS): Volume 25 Issue 1, February 2007
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 2,   Downloads (Overall): 741

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A simple mechanism to increase the utilization of a small trace cache, and simultaneously reduce its power consumption, is presented in this article. The mechanism uses selective storage of traces (filtering) that is based on a new concept in computer architecture: random sampling. The sampling filter exploits the “hot/cold trace” ...
Keywords: Trace cache, power dissipation, sampling filter, cache utilization

13
December 2006 MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 17
Downloads (6 Weeks): 2,   Downloads (12 Months): 18,   Downloads (Overall): 492

Full text available: PDFPDF
The need to reduce power and complexity will increase the interest in Switch on Event multithreading (coarse grained multithreading). Switch On Event multithreading is a low power and low complexity mechanism to improve processor throughput by switching threads on execution stalls. Fairness may, however, become a problem in a mul- ...

14 published by ACM
June 2006 ISMM '06: Proceedings of the 5th international symposium on Memory management
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 2,   Downloads (Overall): 595

Full text available: PDFPDF
Process technology has been driving the computer architecture industry during the last two decades. Until recently, most of the micro-architectures were focused on achieving best performance, usually for a single threaded application, within a given budget of transistors. Recently, power consumption and power density start to be an important factor ...

15
April 2006 International Journal of Parallel Programming: Volume 34 Issue 2, April 2006
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 2

Aggressive prefetching mechanisms improve performance of some important applications, but substantially increase bus traffic and "pressure" on cache tag arrays. They may even reduce performance of applications that are not memory bounded. We introduce a "feedback" mechanism, termed Prefetcher Assessment Buffer (PAB), which filters out requests that are unlikely to ...
Keywords: prefetching, cache tag pressure, memory wall

16 published by ACM
March 2006 ACM SIGARCH Computer Architecture News - Special issue: MEDEA'05: Volume 34 Issue 1, March 2006
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 2,   Downloads (Overall): 106

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We present Inthreads , a computational model aimed at medium-level parallelism. The threads in our model, based on shared architectural registers and having extremely low overheads, are useful for parallelization at a level of a single function call.Inthreads parallelization provides significant speedups, from 35% in case of well-behaved programs to ...

17
September 2005 PACT '05: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 7

This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be effective, the size of the trace cache should be large. Power and timing considerations indicate that a small trace cache is desirable, ...

18 published by ACM
March 2004 ACM SIGARCH Computer Architecture News - ISCA 2004: Volume 32 Issue 2, March 2004
Publisher: ACM
Bibliometrics:
Citation Count: 22
Downloads (6 Weeks): 0,   Downloads (12 Months): 6,   Downloads (Overall): 688

Full text available: PDFPDF
We present the PARROT concept that seeks to achievehigher performance with reduced energy consumptionthrough gradual optimization of frequently executed codetraces. The PARROT microarchitectural framework integratestrace caching, dynamic optimizations and pipelinedecoupling. We employ a selective approach for applyingcomplex mechanisms only upon the most frequently usedtraces to maximize the performance gain at ...
Also published in:
June 2004  ISCA '04: Proceedings of the 31st annual international symposium on Computer architecture

19
December 2003 PACS'03: Proceedings of the Third international conference on Power - Aware Computer Systems
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 3

We present the PARROT concept aimed at both higher performance and power-awareness. The PARROT microarchitectural framework integrates trace caching, dynamic optimizations and pipeline decoupling. We employ a gradual and selective approach for applying complex mechanisms only for the most frequently used traces to maximize the performance gain at any given ...

20
October 2003 IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power: Volume 11 Issue 5, October 2003
Publisher: IEEE Educational Activities Department
Bibliometrics:
Citation Count: 3

Modern computer architectures that support variable length instruction set architectures (ISA), such as the Intel's IA-32, distinguish between the architectural level of presentation and the micro-architectural representations of the instructions. At the micro-architectural level, instructions are represented by fixed-length micro-operations termed uops , and complex instructions are broken into sequence ...
Keywords: performance, power-aware design, cache



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