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 Fred Allison Bower

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Average citations per article11.29
Citation Count79
Publication count7
Publication years2004-2010
Available for download3
Average downloads per article457.00
Downloads (cumulative)1,371
Downloads (12 Months)19
Downloads (6 Weeks)3
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7 results found Export Results: bibtexendnoteacmrefcsv

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1
January 2010
Bibliometrics:
Citation Count: 0

The continued march of technological progress, epitomized by Moore's Law provides the microarchitect with increasing numbers of transistors to employ as we continue to shrink feature geometries. Physical limitations impose new constraints upon designers in the areas of overall power and localized power density. Techniques to scale threshold ...

2
May 2008 IEEE Micro: Volume 28 Issue 3, May 2008
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 21

Although most current multicore processors are homogeneous, microarchitects are now proposing heterogeneous core implementations, including systems in which heterogeneity is introduced at runtime. This article shows that operating system schedulers must consider dynamic heterogeneity or suffer significant power-efficiency and performance losses.
Keywords: multicore, multicore, heterogeneous, scheduling, operating system, power-efficiency, heterogeneous, power-efficiency, scheduling, operating system

3 published by ACM
June 2007 ACM Transactions on Architecture and Code Optimization (TACO): Volume 4 Issue 2, June 2007
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Downloads (Overall): 675

Full text available: PDFPDF
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, ...
Keywords: Hard fault tolerance, fine-grained diagnosis, processor microarchitecture

4 published by ACM
June 2006 ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review: Volume 34 Issue 1, June 2006
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 1,   Downloads (12 Months): 5,   Downloads (Overall): 176

Full text available: PdfPdf
In this paper, we present a new metric, Hard-Fault Architectural Vulnerability Factor (H-AVF), to allow designers to more effectively compare alternate hard-fault tolerance schemes. In order to provide intuition on the use of H-AVF as a metric, we evaluate fault-tolerant level-1 data cache and register file implementations using error correcting ...
Keywords: hard-fault tolerance, computer architecture, reliability
Also published in:
June 2006  SIGMETRICS '06/Performance '06: Proceedings of the joint international conference on Measurement and modeling of computer systems

5
November 2005 MICRO 38: Proceedings of the 38th annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 22
Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Downloads (Overall): 514

Full text available: PDFPDF
We develop a microprocessor design that tolerates hard faults, including fabrication defects and in-field faults, by leveraging existing microprocessor redundancy. To do this, we must: detect and correct errors, diagnose hard faults at the field deconfigurable unit (FDU) granularity, and deconfigure FDUs with hard faults. In our reliable microprocessor design, ...

6
October 2005 IEEE Transactions on Dependable and Secure Computing: Volume 2 Issue 4, October 2005
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 0

To achieve high reliability despite hard faults that occur during operation and to achieve high yield despite defects introduced at fabrication, a microprocessor must be able to tolerate hard faults. In this paper, we present a framework for autonomic self-repair of the array structures in microprocessors (e.g., reorder buffer, instruction ...
Keywords: and microcomputers., microprocessors, Index Terms- Logic design reliability and testing, Index Terms- Logic design reliability and testing, microprocessors, and microcomputers.

7
June 2004 DSN '04: Proceedings of the 2004 International Conference on Dependable Systems and Networks
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 28

In this paper, we present a hardware technique, calledSelf-Repairing Array Structures (SRAS), for maskinghard faults in microprocessor array structures, such asthe reorder buffer and branch history table. SRAS maskserrors that could otherwise lead to slow system recoveries.To detect row errors, every write to a row is mirroredto a dedicated "check ...



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