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 Brad Gene Calder

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Average citations per article28.54
Citation Count3,368
Publication count118
Publication years1993-2012
Available for download62
Average downloads per article591.35
Downloads (cumulative)36,664
Downloads (12 Months)1,477
Downloads (6 Weeks)107
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118 results found Export Results: bibtexendnoteacmrefcsv

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1
June 2012 USENIX ATC'12: Proceedings of the 2012 USENIX conference on Annual Technical Conference
Publisher: USENIX Association
Bibliometrics:
Citation Count: 90

Windows Azure Storage (WAS) is a cloud storage system that provides customers the ability to store seemingly limitless amounts of data for any duration of time. WAS customers have access to their data from anywhere, at any time, and only pay for what they use and store. To provide durability ...

2 published by ACM
October 2011 SOSP '11: Proceedings of the Twenty-Third ACM Symposium on Operating Systems Principles
Publisher: ACM
Bibliometrics:
Citation Count: 137
Downloads (6 Weeks): 35,   Downloads (12 Months): 420,   Downloads (Overall): 4,053

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Windows Azure Storage (WAS) is a cloud storage system that provides customers the ability to store seemingly limitless amounts of data for any duration of time. WAS customers have access to their data from anywhere at any time and only pay for what they use and store. In WAS, data ...
Keywords: cloud storage, Windows Azure, distributed storage systems

3
May 2009 ISHPC '02: Proceedings of the 4th International Symposium on High Performance Computing
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 0

Energy efficient architecture research has flourished recently, in an attempt to address packaging and cooling concerns of current microprocessor designs, as well as battery life for mobile computers. Moreover, architects have become increasingly concerned with the complexity of their designs in the face of scalability, verification, and manufacturing concerns. In ...

4
May 2009 ISHPC '02: Proceedings of the 4th International Symposium on High Performance Computing
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 1

The Itanium processor, an implementation of an Explicitly Parallel Instruction Computing (EPIC) architecture, is an in-order processor that fetches, executes, and forwards results to functional units in-order. The architecture relies heavily on the compiler to expose Instruction Level Parallelism (ILP) to avoid stalls created by in-order processing. The goal of ...

5 published by ACM
May 2008 GLSVLSI '08: Proceedings of the 18th ACM Great Lakes symposium on VLSI
Publisher: ACM
Bibliometrics:
Citation Count: 12
Downloads (6 Weeks): 0,   Downloads (12 Months): 12,   Downloads (Overall): 222

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Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in an application-based tuning methodology. Prior work and logic suggests phase-based tuning may provide significant savings over application-based tuning. We investigate this hypothesis using a detailed cache ...
Keywords: phase prediction, phase-based reconfiguration, phase-based tuning, caches, configurable architecture, configurable caches, cache tuning

6
September 2007 IISWC '07: Proceedings of the 2007 IEEE 10th International Symposium on Workload Characterization
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 3

Almost all new consumer-grade processors are capable of executing multiple programs simultaneously. The analysis of multiprogrammed workloads for multicore and SMT processors is challenging and time-consuming because there are many possible combinations of benchmarks to execute and each combination may exhibit several different interesting behaviors. Missing particular combinations of program ...

7
September 2007 PACT '07: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 1,   Downloads (12 Months): 2,   Downloads (Overall): 137

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Performance auditing is an online optimization strategy that empirically measures the effectiveness of an optimization on a particular code region. It has the potential to greatly improve performance and prevent degradations due to compiler optimizations. Performance auditing relies on the ability to obtain sufficiently many timings of the region of ...

8 published by ACM
June 2007 PLDI '07: Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation
Publisher: ACM
Bibliometrics:
Citation Count: 100
Downloads (6 Weeks): 9,   Downloads (12 Months): 49,   Downloads (Overall): 1,021

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Many concurrency bugs in multi-threaded programs are due to dataraces. There have been many efforts to develop static and dynamic mechanisms to automatically find the data races. Most of the prior work has focused on finding the data races and eliminating the false positives. In this paper, we instead focus ...
Keywords: benign data races, replay, concurrency Bbugs
Also published in:
June 2007  ACM SIGPLAN Notices - Proceedings of the 2007 PLDI conference: Volume 42 Issue 6, June 2007

9
April 2007 DATE '07: Proceedings of the conference on Design, automation and test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Downloads (Overall): 139

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Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or temporal redundancy to achieve fault tolerance. Though they can provide complete fault coverage, they incur significant hardware and/or performance cost. It is desirable to ...

10
February 2007 HPCA '07: Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 17

Speculative precomputation enables effective cache prefetching for even irregular memory access behavior, by using an alternate thread on a multithreaded or multi-core architecture. This paper describes a system that constructs and runs precomputation based prefetching threads via event-driven dynamic optimization. Precomputation threads are dynamically constructed by a runtime compiler from ...

11
January 2007 HiPEAC'07: Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 2

We analyze the performance of different bounds checking implementations. Specifically, we examine using the x86 bound instruction to reduce the run-time overhead. We also propose a compiler optimization that prunes the bounds checks that are not necessary to guarantee security. The optimization is based on the observation that buffer overflow ...

12
January 2007 IEEE Micro: Volume 27 Issue 1, January 2007
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 14

Equipping processors with programmable hardware to patch design errors lets manufacturers release regular hardware patches, avoiding costly chip recalls and potentially speeding time to market. For each error detected, the manufacturer creates a fingerprint, which the customer uses to program the hardware. The hardware watches for error conditions; when they ...
Keywords: hardware errors, hardware errors, microarchitecture for fault-tolerance, design defects in real processors, processor errata analysis, microarchitecture for fault-tolerance, design defects in real processors, processor errata analysis

13
December 2006 MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 15
Downloads (6 Weeks): 0,   Downloads (12 Months): 14,   Downloads (Overall): 571

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We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vector machines. Parallelizing code in this manner leads to a high frequency of barriers, and we explore the impact of different barrier mechanisms upon ...

14
December 2006 The Journal of Machine Learning Research: Volume 7, 12/1/2006
Publisher: JMLR.org
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 0,   Downloads (12 Months): 7,   Downloads (Overall): 335

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An essential step in designing a new computer architecture is the careful examination of different design options. It is critical that computer architects have efficient means by which they may estimate the impact of various design options on the overall machine. This task is complicated by the fact that different ...

15
November 2006 Computer: Volume 39 Issue 11, November 2006
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 16

Improving the infrastructure, benchmarking, and methodology of simulation--the dominant computer performance evaluation method--will result in higher efficiency and let architects gain more insight into processor behavior.
Keywords: Computer performance evaluation, Simulation, Processor performance, Simulation, Computer performance evaluation, Processor performance

16 published by ACM
October 2006 ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Publisher: ACM
Bibliometrics:
Citation Count: 57
Downloads (6 Weeks): 0,   Downloads (12 Months): 19,   Downloads (Overall): 693

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Significant time is spent by companies trying to reproduce and fix bugs. BugNet and FDR are recent architecture proposals that provide architecture support for deterministic replay debugging. They focus on continuously recording information about the program's execution, which can be communicated back to the developer. Using that information, the developer ...
Keywords: dependencies, replay, shared memory, strata, debugging, logging
Also published in:
October 2006  ACM SIGOPS Operating Systems Review - Proceedings of the 2006 ASPLOS Conference: Volume 40 Issue 5, December 2006 November 2006  ACM SIGPLAN Notices - Proceedings of the 2006 ASPLOS Conference: Volume 41 Issue 11, November 2006 October 2006  ACM SIGARCH Computer Architecture News - Proceedings of the 2006 ASPLOS Conference: Volume 34 Issue 5, December 2006

17 published by ACM
October 2006 ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Publisher: ACM
Bibliometrics:
Citation Count: 33
Downloads (6 Weeks): 0,   Downloads (12 Months): 21,   Downloads (Overall): 772

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Exploiting thread level parallelism is paramount in the multicore era. Transactions enable programmers to expose such parallelism by greatly simplifying the multi-threaded programming model. Virtualized transactions (unbounded in space and time) are desirable, as they can increase the scope of transactions' use, and thereby further simplify a programmer's job. However, ...
Keywords: parallel programming, concurrency, transactional memory, transactions, virtual memory
Also published in:
October 2006  ACM SIGOPS Operating Systems Review - Proceedings of the 2006 ASPLOS Conference: Volume 40 Issue 5, December 2006 November 2006  ACM SIGPLAN Notices - Proceedings of the 2006 ASPLOS Conference: Volume 41 Issue 11, November 2006 October 2006  ACM SIGARCH Computer Architecture News - Proceedings of the 2006 ASPLOS Conference: Volume 34 Issue 5, December 2006

18
July 2006 IEEE Micro: Volume 26 Issue 4, July 2006
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 3

Sampling techniques dramatically shorten simulation times for industry-standard benchmarks, but establishing the correct architecture and microarchitecture states at the beginning of each sample can be time-consuming. This article compares the accuracy and speed of various sampling startup techniques, introducing touched memory image and memory hierarchy state. Together, these two techniques ...
Keywords: sampling, warmup, checkpoints, computer architecture, computer architecture, simulation, sampling, warmup, checkpoints, SimPoint, simulation, SimPoint

19 published by ACM
June 2006 ACM SIGMETRICS Performance Evaluation Review - Performance evaluation review: Volume 34 Issue 1, June 2006
Publisher: ACM
Bibliometrics:
Citation Count: 29
Downloads (6 Weeks): 1,   Downloads (12 Months): 10,   Downloads (Overall): 568

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Modern architecture research relies heavily on application-level detailed pipeline simulation. A time consuming part of building a simulator is correctly emulating the operating system effects, which is required even if the goal is to simulate just the application code, in order to achieve functional correctness of the application's execution. Existing ...
Keywords: architecture simulation, emulating system calls, checkpoints
Also published in:
June 2006  SIGMETRICS '06/Performance '06: Proceedings of the joint international conference on Measurement and modeling of computer systems

20 published by ACM
June 2006 ACM SIGPLAN Notices - Proceedings of the 2006 PLDI Conference: Volume 41 Issue 6, June 2006
Publisher: ACM
Bibliometrics:
Citation Count: 24
Downloads (6 Weeks): 1,   Downloads (12 Months): 23,   Downloads (Overall): 692

Full text available: PDFPDF
As hardware complexity increases and virtualization is added at more layers of the execution stack, predicting the performance impact of optimizations becomes increasingly difficult. Production compilers and virtual machines invest substantial development effort in performance tuning to achieve good performance for a range of benchmarks. Although optimizations typically perform well ...
Keywords: virtual machines, Java, feedback-directed optmizations
Also published in:
June 2006  PLDI '06: Proceedings of the 27th ACM SIGPLAN Conference on Programming Language Design and Implementation



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