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 Peter Frank Corbett

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Average citations per article13.27
Citation Count199
Publication count15
Publication years1986-1996
Available for download4
Average downloads per article398.75
Downloads (cumulative)1,595
Downloads (12 Months)25
Downloads (6 Weeks)5
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1 published by ACM
August 1996 ACM Transactions on Computer Systems (TOCS): Volume 14 Issue 3, Aug. 1996
Publisher: ACM
Citation Count: 56
Downloads (6 Weeks): 4,   Downloads (12 Months): 20,   Downloads (Overall): 961

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The Vesta parallel file system is designed to provide parallel file access to application programs running on multicomputers with parallel I/O subsystems. Vesta uses a new abstraction of files: a file is not a sequence of bytes, but rather it can be partitioned into multiple disjoint sequences that are accessed ...
Keywords: parallel computing, parallel file system, data partitioning

September 1995 IEEE Parallel & Distributed Technology: Systems & Technology: Volume 3 Issue 3, September 1995
Publisher: IEEE Computer Society Press
Citation Count: 7

Applications on MPPs often require a high aggregate bandwidth of low-latency I/O to secondary storage. This requirement can met by internal parallel I/O subsystems that comprise dedicated I/O nodes, each with processor, memory, and disks.Massively parallel processors (MPPs), encompassing from tens to thousands of processors, are emerging as a major ...

April 1995 IPPS '95: Proceedings of the 9th International Symposium on Parallel Processing
Publisher: IEEE Computer Society
Citation Count: 4

Vesta is an experimental parallel file system implemented on the IBM SPI. Its main features are support for parallel access from multiple application processes to file, and the ability to partition and re-partition the file data among these processes. This paper reports on a set of experiments designed to evaluate ...
Keywords: parallel file system, performance, performance evaluation, file organisation, orthogonal partitioning, parallel processing, single-node performance, bandwidth scales, prefetching, Vesta parallel file system, parallel access

April 1995 IBM Systems Journal: Volume 34 Issue 2, 1995
Publisher: IBM Corp.
Citation Count: 35

June 1994 Interconnection networks for high-performance parallel computers
Publisher: IEEE Computer Society Press
Citation Count: 0

6 published by ACM
December 1993 Supercomputing '93: Proceedings of the 1993 ACM/IEEE conference on Supercomputing
Publisher: ACM
Citation Count: 32

7 published by ACM
December 1993 ACM SIGARCH Computer Architecture News - Special issue on input/output in parallel computer systems: Volume 21 Issue 5, Dec. 1993
Publisher: ACM
Citation Count: 12
Downloads (6 Weeks): 1,   Downloads (12 Months): 1,   Downloads (Overall): 251

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The Vesta parallel file system provides parallel access from compute nodes to files distributed across I/O nodes in a massively parallel computer. Vesta is intended to solve the I/O problems of massively parallel computers executing numerically intensive scientific applications. Vesta has three interesting characteristics: First, it provides a user defined ...

September 1992 IEEE Transactions on Parallel and Distributed Systems: Volume 3 Issue 5, September 1992
Publisher: IEEE Press
Citation Count: 6

A sorting algorithm, dubbed MeshSort, for multidimensional mesh-connected multiprocessors is introduced. Bitonic Sort and ShearSort are shown to be special cases of MeshSort. MeshSort thus provides some insight into the operation of parallel sorting. It requires operations only along orthogonal vectors of processors, simplifying the control of the multiprocessor. This ...
Keywords: Bitonic Sort, Index Termssorting algorithm, multidimensional mesh-connected multiprocessors, multiprocessor interconnection networks, orthogonal vectors, parallel algorithms, FastMeshSort, ShearSort, multidimensional memory structure, parallel sorting, reduced architecture, MeshSort, routing algorithm, sorting

September 1992 IEEE Transactions on Parallel and Distributed Systems: Volume 3 Issue 5, September 1992
Publisher: IEEE Press
Citation Count: 27

Rotator graphs, a set of directed permutation graphs, are proposed as an alternative to star and pancake graphs. Rotator graphs are defined in a way similar to the recently proposed Faber-Moore graphs. They have smaller diameter, n-1 in a graph with n factorial vertices, than either the star or pancake ...
Keywords: fault tolerant, one-step fault diagnosable, optimal routing algorithm, rotator graphs, point-to-point multiprocessor networks, Faber-Moore graphs, multiprocessor interconnection networks, Hamiltonian circuit, Index Termstopology, directed graphs, directed permutation graphs

February 1991 Information Processing Letters: Volume 37 Issue 4, Feb. 28, 1991
Publisher: Elsevier North-Holland, Inc.
Citation Count: 2

December 1990 Journal of Parallel and Distributed Computing: Volume 11 Issue 1, Jan. 1991
Publisher: Academic Press, Inc.
Citation Count: 5

January 1990
Citation Count: 1

Many existing and proposed multiprocessors are interconnected using network topologies describable by simple mathematical relationships. This thesis deals with several aspects of interconnection networks for highly parallel computers. Point-to-point and multistage interconnection schemes are discussed, with application made to multiprocessors with both highly synchronized and highly autonomous processors. Algorithmic aspects ...

13 published by ACM
December 1989 ACM SIGARCH Computer Architecture News: Volume 17 Issue 6, Dec. 1989
Publisher: ACM
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 116

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We describe a construction technique for orthogonal multiprocessors, based on a definition of the inner product and the orthogonality of binary vectors. Orthogonal networks include spanning bus hypermeshes. A measure of communications overhead in parallel processing systems is defined as a function of algorithm and architecture. Its dependence on the ...

June 1988 DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference
Publisher: IEEE Computer Society Press
Citation Count: 11
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 267

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A new silicon compiler is described, called PARSIFAL (not an acronym). It constructs chips with a data flow architecture in which data is passed in a digit-wide pipeline from one computational element to the next. The size of a digit may be specified by the user to be any value ...

December 1986 Microprocessing and Microprogramming: Volume 18 Issue 1-5, Dec. 1986
Publisher: Elsevier Science Publishers B. V.
Citation Count: 0

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