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 Robert King Brayton

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Average citations per article13.27
Citation Count3,304
Publication count249
Publication years1961-2016
Available for download133
Average downloads per article203.37
Downloads (cumulative)27,048
Downloads (12 Months)972
Downloads (6 Weeks)120
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251 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
November 2016 ICCAD '16: Proceedings of the 35th International Conference on Computer-Aided Design
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 3,   Downloads (12 Months): 41,   Downloads (Overall): 41

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Lexicographic Boolean satisfiability (LEXSAT) is a variation of the Boolean satisfiability problem (SAT). Given a variable order, LEXSAT finds a satisfying assignment whose integer value under the given variable order is minimum (maximum) among all satisfiable assignments. If the formula has no satisfying assignments, LEXSAT proves it unsatisfiable, as does ...

2
October 2016 FMCAD '16: Proceedings of the 16th Conference on Formal Methods in Computer-Aided Design
Publisher: FMCAD Inc
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 5,   Downloads (Overall): 5

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Methods for word-level model checking based on purely bit-level techniques have difficulties with heavy arithmetic logic. Word-level and SMT approaches often are limited by relying on (incomplete) bounded model checking. UFAR, a hybrid word- and bit-level approach, addresses these issues, taking advantage of modern bit-level sequential techniques while heavy arithmetic ...

3
September 2015 FMCAD '15: Proceedings of the 15th Conference on Formal Methods in Computer-Aided Design
Publisher: FMCAD Inc
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 12,   Downloads (Overall): 12

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Reverse engineering is the extraction of word level information from a gate-level netlist. It has applications in formal verification, hardware trust, information recovery, and general technology mapping. A preprocessing step finds blocks in a circuit in which word level components are expected. A second step searches for word level components ...

4
September 2015 Revised Selected Papers of the SEFM 2015 Collocated Workshops on Software Engineering and Formal Methods - Volume 9509
Publisher: Springer-Verlag New York, Inc.
Bibliometrics:
Citation Count: 0

We address the problem of the automatic design of automata to translate between different protocols, and we reduce it to the solution of equations defined over regular languages and finite automata FA/finite state machines FSMs. The largest solution of the defined language equations includes all protocol converters that solve the ...

5
August 2015 DSD '15: Proceedings of the 2015 Euromicro Conference on Digital System Design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

We study three-level implementations where the first two levels represent a standard PLA form with an ANDplane and an OR-plane. This implements a 2m-output SOP. The final stage consists of m two-input programmable LUTs. The PLA outputs are paired so that the LUT outputs implement a set of m given ...

6 published by ACM
June 2015 DAC '15: Proceedings of the 52nd Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 26,   Downloads (Overall): 89

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Sequential clock-gating can lead to easier equivalence checking problems, compared to the general sequential equivalence checking (SEC) problem. Modern sequential clock-gating techniques introduce control structures to disable unnecessary clocking. This violates combinational equivalence but maintains sequential equivalence between the original and revised circuits. We propose the use of characteristic graphs ...
Keywords: clock-gating, model checking, equivalence checking

7 published by ACM
February 2015 FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 3,   Downloads (12 Months): 31,   Downloads (Overall): 129

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Field-Programmable Gate Arrays (FPGA) implement logic functions using programmable cells, such as K-input lookup-tables (K-LUTs). A K-LUT can implement any Boolean function with K inputs and one output. Methods for mapping into K-LUTs are extensively researched and widely used. Recently, cells other than K LUTs have been explored, for example, ...
Keywords: fpga, technology mapping, boolean function, programmable cells, boolean matching

8 published by ACM
September 2014 BCB '14: Proceedings of the 5th ACM Conference on Bioinformatics, Computational Biology, and Health Informatics
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 9,   Downloads (Overall): 27

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We present NINJA, a suite of computational techniques for modelling and formally verifying properties of tiered-rate chemical reaction networks.
Keywords: chemical reaction networks, formal verification, model checking

9
February 2014 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Volume 33 Issue 2, February 2014
Publisher: IEEE Press
Bibliometrics:
Citation Count: 1

Sequential logic synthesis often leads to substantially easier equivalence checking problems, compared to general-case sequential equivalence checking (SEC). This paper theoretically investigates when SEC can be reduced to a combinational equivalence checking (CEC) problem. It shows how the theory can be applied when sequential transforms are used, such as sequential ...

10
January 2014
Bibliometrics:
Citation Count: 0

The Problem of the Unknown Component: Theory and Applications addresses the issue of designing a component that, combined with a known part of a system, conforms to an overall specification. The authors tackle this problem by solving abstract equations over a language. The most general solutions are studied when both ...

11
March 2013 DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 1,   Downloads (12 Months): 3,   Downloads (Overall): 44

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Verification benefits from removing logic that is not relevant for a proof. Techniques for doing this are known as localization abstraction . Abstraction is often performed by selecting a subset of gates to be included in the abstracted model; the signals feeding into this subset become unconstrained cut-points. In this ...

12
March 2013 DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1,   Downloads (12 Months): 6,   Downloads (Overall): 42

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In numerous EDA flows, time-consuming computations are repeatedly applied to sequential circuits. This motivates developing methods to determine what circuits have been processed already by a tool. This paper proposes an algorithm for semi-canonical labeling of nodes in a sequential AIG, allowing problems or sub-problems solved by an EDA tool ...

13
October 2012
Bibliometrics:
Citation Count: 1

Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs). The first volume, Synthesis of Finite State Machines: Functional Optimization, addresses functional optimization, whereas this one addresses logic optimization. The result of functional optimization is ...

14
March 2012 DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 2,   Downloads (12 Months): 6,   Downloads (Overall): 20

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Formal verification of liveness properties of practical communication fabrics are generally intractable with present day verification tools. We focus on a particular type of liveness called 'progress' which is a form of deadlock freedom. An end-to-end progress property is broken down into localized safety assertions, which are more easily provable, ...

15
March 2012 DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Downloads (Overall): 36

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Mapping into K-input lookup tables (K-LUTs) is an important step in synthesis for Field-Programmable Gate Arrays (FPGAs). The traditional FPGA architecture assumes all interconnects between individual LUTs are "routable". This paper proposes a modified FPGA architecture which allows for direct (non-routable) connections between adjacent LUTs. As a result, delay can ...

16 published by ACM
December 2011 ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 4 Issue 4, December 2011
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 4,   Downloads (12 Months): 22,   Downloads (Overall): 213

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We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability. The proposed resynthesis (a) is capable of substantial logic restructuring, (b) is customizable to solve a variety of optimization tasks, and (c) has reasonable runtime on industrial designs. The approach uses don't-cares computed for a ...
Keywords: don't-cares, resynthesis, Boolean satisfiability, FPGA

17
November 2011 ICCAD '11: Proceedings of the International Conference on Computer-Aided Design
Publisher: IEEE Press
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1,   Downloads (12 Months): 3,   Downloads (Overall): 44

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Reducing delay of a digital circuit is an important topic in logic synthesis for standard cells and LUT-based FPGAs. This paper presents a simple, fast, and very efficient synthesis algorithm to improve the delay after technology mapping. The algorithm scales to large designs and is implemented in a publicly-available technology ...

18
November 2011 ICCAD '11: Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Reducing delay of a digital circuit is an important topic in logic synthesis for standard cells and LUT-based FPGAs. This paper presents a simple, fast, and very efficient synthesis algorithm to improve the delay after technology mapping. The algorithm scales to large designs and is implemented in a publicly-available technology ...

19
October 2011 FMCAD '11: Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Publisher: FMCAD Inc
Bibliometrics:
Citation Count: 50
Downloads (6 Weeks): 6,   Downloads (12 Months): 73,   Downloads (Overall): 192

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Last spring, in March 2010, Aaron Bradley published the first truly new bit-level symbolic model checking algorithm since Ken McMillan's interpolation based model checking procedure introduced in 2003. Our experience with the algorithm suggests that it is stronger than interpolation on industrial problems, and that it is an important algorithm ...

20
December 2010
Bibliometrics:
Citation Count: 1

Synthesis of Finite State Machines: Functional Optimization is one of two monographs devoted to the synthesis of Finite State Machines (FSMs). This volume addresses functional optimization, whereas the second addresses logic optimization. By functional optimization here we mean the body of techniques that: compute all permissible sequential functions for a ...



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