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 Jichuan Chang

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Average citations per article27.38
Citation Count219
Publication count8
Publication years2004-2015
Available for download6
Average downloads per article825.83
Downloads (cumulative)4,955
Downloads (12 Months)234
Downloads (6 Weeks)29
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8 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
October 2015 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 3, October 2015
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 5,   Downloads (12 Months): 45,   Downloads (Overall): 174

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Motivated by the challenges of scaling up memory capacity and fully exploiting the benefits of memory compression, we propose Buri, a hardware-based memory compression scheme, which simultaneously achieves cost efficiency, high performance, and ease of adoption. Buri combines (1) a self-contained, ready-to-adopt hardware compression module, which manages metadata compression and ...
Keywords: Memory, performance, big data, compression, scalability

2 published by ACM
June 2014 ACM International Conference on Supercomputing 25th Anniversary Volume
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 16,   Downloads (Overall): 60

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In this paper, we reflect on our experiences and the lessons learned in designing and evaluating the cooperative cache partitioning technique for chip multiprocessors.
Keywords: performance, algorithms, design, management

3 published by ACM
June 2007 ICS '07: Proceedings of the 21st annual international conference on Supercomputing
Publisher: ACM
Bibliometrics:
Citation Count: 89
Downloads (6 Weeks): 2,   Downloads (12 Months): 20,   Downloads (Overall): 1,288

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This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a single spatial partition repeatedly throughout a stable program phase, CCP resolves cache contention with multiple time-sharing partitions. Timesharing cache resources among partitions allows each thrashing thread ...
Keywords: CMP, QoS, fairness, cooperative cache partitioning, multiple time-sharing partitions

4 published by ACM
June 2007 ACM International Conference on Supercomputing 25th Anniversary Volume
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 14,   Downloads (12 Months): 92,   Downloads (Overall): 376

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This paper presents Cooperative Cache Partitioning (CCP) to allocate cache resources among threads concurrently running on CMPs. Unlike cache partitioning schemes that use a single spatial partition repeatedly throughout a stable program phase, CCP resolves cache contention with multiple time-sharing partitions. Timesharing cache resources among partitions allows each thrashing thread ...
Keywords: CMP, QoS, fairness, cooperative cache partitioning, multiple time-sharing partitions

5
January 2007
Bibliometrics:
Citation Count: 0

Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these challenges, we propose CMP cooperative caching (CC), a unified framework to efficiently organize ...

6
May 2006 ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 100
Downloads (6 Weeks): 7,   Downloads (12 Months): 37,   Downloads (Overall): 2,091

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This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's aggregate on-chip cache resources. Cooperative caching combines the strengths of private and shared cache organizations by forming an aggregate "shared" cache through cooperation among private caches. Locally active data are attracted to the private caches by their ...
Also published in:
May 2006  ACM SIGARCH Computer Architecture News: Volume 34 Issue 2, May 2006

7
November 2004 IEEE Micro: Volume 24 Issue 6, November 2004
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 3

Coherence decoupling is a microarchitectural mechanism that implements separate protocols for speculative use and for the eventual verification of values. The technique reduces the effect of long communication latencies while mitigating the burdens on the coherence protocol designer and the parallel programmer.

8 published by ACM
October 2004 ASPLOS XI: Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Publisher: ACM
Bibliometrics:
Citation Count: 22
Downloads (6 Weeks): 0,   Downloads (12 Months): 24,   Downloads (Overall): 966

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This paper explores a new technique called coherence decoupling , which breaks a traditional cache coherence protocol into two protocols: a Speculative Cache Lookup (SCL) protocol and a safe, backing coherence protocol. The SCL protocol produces a speculative load value, typically from an invalid cache line, permitting the processor to ...
Keywords: speculative cache lookup, coherence decoupling, coherence misses, false sharing
Also published in:
November 2004  ACM SIGPLAN Notices - ASPLOS '04: Volume 39 Issue 11, November 2004 December 2004  ACM SIGARCH Computer Architecture News - ASPLOS 2004: Volume 32 Issue 5, December 2004 December 2004  ACM SIGOPS Operating Systems Review - ASPLOS '04: Volume 38 Issue 5, December 2004



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