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 Zhigang Hu

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Average citations per article31.58
Citation Count600
Publication count19
Publication years2000-2008
Available for download10
Average downloads per article659.30
Downloads (cumulative)6,593
Downloads (12 Months)214
Downloads (6 Weeks)20
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19 results found Export Results: bibtexendnoteacmrefcsv

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1
January 2008 ASP-DAC '08: Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 8
Downloads (6 Weeks): 0,   Downloads (12 Months): 4,   Downloads (Overall): 504

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Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual ...

2
June 2007 DSN '07: Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 17

This paper tackles the issue of modeling chip lifetime reliability at the architecture level. We propose a new and robust structure-aware lifetime reliability model at the architecture-level, where devices only vulnerable to failure mechanisms and the effective stress condition of these devices are taken into account for the failure rate ...

3
January 2007 VLSID '07: Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

The details of the power distribution of state of the art CMOS chips (e.g., local regions of high power (or hotspots), which disproportionally drive up junction temperatures) can have a severe impact on reliability, manufacturing yield and chip performances. In this paper we discuss the results of a recently developed ...

4 published by ACM
August 2005 ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 0,   Downloads (12 Months): 4,   Downloads (Overall): 163

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This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of power dissipation, and both design styles and various clock gating schemes can be found in modern, high-performance processors. Although some work in ...
Keywords: architecture, temperature, power, clock gating

5
February 2005 HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 55

Simultaneous multithreading (SMT) and chip multi-processing (CMP) both allow a chip to achieve greater throughput, but their relative energy-efficiency and thermal properties are still poorly understood. This paper uses Turandot, PowerTimer, and HotSpot to explore this design space for a POWER4/POWER5-like core. For an equal-area comparison with this style of ...

6
February 2005 HPCA '05: Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 15

Clock-gating has been introduced as the primary means of dynamic power management in recent high-end commercial microprocessors. The temperature drop resulting from active power reduction can result in additional leakage power savings in future processors. In this paper we first examine the realistic benefits and limits of clock-gating in current ...

7 published by ACM
August 2004 ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design
Publisher: ACM
Bibliometrics:
Citation Count: 19
Downloads (6 Weeks): 3,   Downloads (12 Months): 31,   Downloads (Overall): 314

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Simultaneous multithreading (SMT) has proven to be an effective method of increasing the performance of microprocessors by extracting additional instruction-level parallelism from multiple threads. In current microprocessor designs, power-efficiency is of critical importance, and we present modeling extensions to an architectural simulator to allow us to study the power-performance efficiency ...
Keywords: multithreading

8 published by ACM
August 2004 ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design
Publisher: ACM
Bibliometrics:
Citation Count: 99
Downloads (6 Weeks): 7,   Downloads (12 Months): 83,   Downloads (Overall): 1,934

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Leakage power is a major concern in current and future microprocessor designs. In this paper, we explore the potential of architectural techniques to reduce leakage through power-gating of execution units. This paper first develops parameterized analytical equations that estimate the break-even point for application of power-gating techniques. The potential for ...
Keywords: low power, microarchitecture, execution units, power-gating

9 published by ACM
June 2004 ACM Transactions on Architecture and Code Optimization (TACO): Volume 1 Issue 2, June 2004
Publisher: ACM
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 0,   Downloads (12 Months): 9,   Downloads (Overall): 636

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With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors. Recent work has suggested that larger, aggressive branch predictors can and should be used in order to improve microprocessor performance. A further consideration is that ...
Keywords: Energy aware computing

10
February 2003 HPCA '03: Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 18

Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recently, sophisticated hardware correlating prefetching mechanisms have been proposed, in some cases coupled with some form of dead-block prediction. In many proposals, however, correlating ...

11 published by ACM
August 2002 ISLPED '02: Proceedings of the 2002 international symposium on Low power electronics and design
Publisher: ACM
Bibliometrics:
Citation Count: 12
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 181

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Much of on-chip storage is devoted to transient, often short-lived, data. Despite this, virtually all on-chip array structures use six-transistor (6T) static RAM cells that store data indefinitely. In this paper we propose the use of quasi-static four-transistor (4T) RAM cells. Quasi-static 4T cells provide both energy and area savings. ...
Keywords: 4T, memory cell, decay, leakage power, quasi-static, transient data

12 published by ACM
May 2002 ACM SIGARCH Computer Architecture News - Special Issue: Proceedings of the 29th annual international symposium on Computer architecture (ISCA '02): Volume 30 Issue 2, May 2002
Publisher: ACM
Bibliometrics:
Citation Count: 51
Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Downloads (Overall): 646

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Techniques for analyzing and improving memory referencing behavior continue to be important for achieving good overall program performance due to the ever-increasing performance gap between processors and main memory. This paper offers a fresh perspective on the problem of predicting and optimizing memory behavior. Namely, we show quantitatively the extent ...
Keywords: memory hierachy, time-based techniques, timekeeping prefetching, conflict miss identification, dead block prediction, victim cache filtering
Also published in:
May 2002  ISCA '02: Proceedings of the 29th annual international symposium on Computer architecture

13 published by ACM
May 2002 ACM Transactions on Computer Systems (TOCS): Volume 20 Issue 2, May 2002
Publisher: ACM
Bibliometrics:
Citation Count: 18
Downloads (6 Weeks): 2,   Downloads (12 Months): 9,   Downloads (Overall): 372

Full text available: PDFPDF
Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to high-performance processors for highend servers. Although the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect that in future chip ...
Keywords: leakage power, Cache memories, cache decay, generational behavior

14
January 2002 IEEE Computer Architecture Letters: Volume 1 Issue 1, January 2002
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

This paper proposes the use of four-transistor (4T) cacheand branch predictor array cell designs to address increasingworries regarding leakage power dissipation. While 4T designslose state when infrequently accessed, they have very lowleakage, smaller area, and no capacitive loads to switch. Thisshort paper gives an overview of 4T implementation issues anda ...

15

16 published by ACM
November 2001 CASES '01: Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Publisher: ACM
Bibliometrics:
Citation Count: 20
Downloads (6 Weeks): 1,   Downloads (12 Months): 8,   Downloads (Overall): 798

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In the DSP world, many media workloads have to perform a specific amount of work in a specific period of time. This observation led us to examine Simultaneous Multithreading (SMT) and Chip Multiprocessing (CMP) for a VLIW DSP architecture (specifically the Star*Core SC140), in conjunction with Frequency/Voltage scaling to decrease ...

17
October 2001
Bibliometrics:
Citation Count: 1

This paper shows that substantial reductions in leakage energy can be obtained by deactivating groups of branch-predictor entries if they lie idle for a sufficiently long time. Decay techniques, first introduced by Kaxiras et al. for caches, work by tracking accesses to cache lines and turning off power to those ...

18 published by ACM
May 2001 ISCA '01: Proceedings of the 28th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 248
Downloads (6 Weeks): 6,   Downloads (12 Months): 55,   Downloads (Overall): 1,045

Full text available: PDFPDF
Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to high-performance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power, leakage power is also beginning to be a concern. Chipmakers expect that in future chip ...
Also published in:
May 2001  ACM SIGARCH Computer Architecture News - Special Issue: Proceedings of the 28th annual international symposium on Computer architecture (ISCA '01): Volume 29 Issue 2, May 2001

19
November 2000 PACS '00: Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 8

Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we explore an architectural idea to reduce leakage power in data caches. Previous work has shown that cache frames are "dead" for a significant ...



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