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 Jan Kuper

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Average citations per article2.55
Citation Count79
Publication count31
Publication years1993-2016
Available for download12
Average downloads per article137.67
Downloads (cumulative)1,652
Downloads (12 Months)134
Downloads (6 Weeks)14
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31 results found Export Results: bibtexendnoteacmrefcsv

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1
March 2016 DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 0

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The POLCA project develops annotations on fragments of imperative code to guide program transformations for better utilization of resources. These annotations express the computational essence of the code fragments without referring to memory usage or execution time. That makes the annotations mathematical in nature such that provably correct transformations can ...
Keywords: formal methods, program transformations, code partitioning, optimization

2 published by ACM
December 2015 ACM Transactions on Embedded Computing Systems (TECS): Volume 14 Issue 4, December 2015
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 15,   Downloads (Overall): 76

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In this article, we present a mathematical characterisation of admissible schedules of cyclo-static dataflow ( csdf ) graphs. We demonstrate how algebra ic manipulation of this characterization is related to unfolding csdf actors and how this manipulation allows csdf graphs to be transformed into mrsdf graphs that are equivalent , ...
Keywords: dataflow graphs, Analysis, cyclo-static synchronous

3
September 2015 CLUSTER '15: Proceedings of the 2015 IEEE International Conference on Cluster Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

This paper presents a programming model approach that explicitly addresses the programmability of scientific code by annotating imperative code with its algorithmic structural behavior. This information is used to create hierarchical structures, as opposed to the flat structure that most programming models work with, which allows sound code transformation at ...
Keywords: Programming models, HPC, embedded systems, code transformation, compilers, parallelization

4
June 2014 ACSD '14: Proceedings of the 2014 14th International Conference on Application of Concurrency to System Design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

In this paper, we present a transformation that takes a cyclo-static dataflow (CSDF) graph and produces an equivalent multi-rate synchronous dataflow (MRSDF) graph. This fills a gap in existing analysis techniques for synchronous dataflow graphs, transformations into equivalent homogeneous synchronous dataflow (HSDF) graphs exist, but these suffer from an exponential ...
Keywords: synchronous dataflow, transformation, analysis

5 published by ACM
June 2014 SCOPES '14: Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 6,   Downloads (Overall): 67

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Exact analysis of synchronous dataflow (sdf) graphs is often considered too costly, because of the expensive transformation of the graph into a single-rate equivalent. As an alternative, several authors have proposed approximate analyses. Existing approaches to approximation are based on the operational semantics of an sdf graph. We propose an ...
Keywords: synchronous dataflow, transformation, approximation

6
February 2014 PDP '14: Proceedings of the 2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to implement, it is ...
Keywords: Dynamic voltage and frequency scaling, energy minimization, mathematical programming, parallel processing

7
May 2013 TFP 2013: Revised Selected Papers of the 14th International Symposium on Trends in Functional Programming - Volume 8322
Publisher: Springer-Verlag New York, Inc.
Bibliometrics:
Citation Count: 2

A straightforward synthesis from functional languages to digital circuits transforms variables to wires. The types of these variables determine the bit-width of the wires. Assigning a bit-width to polymorphic and function-type variables within this direct synthesis scheme is impossible. Using a term rewrite system, polymorphic and function-type binders can be ...

8 published by ACM
January 2013 ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers: Volume 9 Issue 4, January 2013
Publisher: ACM
Bibliometrics:
Citation Count: 11
Downloads (6 Weeks): 6,   Downloads (12 Months): 52,   Downloads (Overall): 419

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Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are popular techniques for reducing energy consumption. Algorithms for optimal DVFS exist, but optimal DPM and the optimal combination of DVFS and DPM are not yet solved. In this article we use well-established models of DPM and DVFS for ...
Keywords: Dynamic power management, energy minimization, dynamic voltage and frequency scaling

9
September 2012 SEAA '12: Proceedings of the 2012 38th Euromicro Conference on Software Engineering and Advanced Applications
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 7

In this paper we present a novel approach to throughput analysis of synchronous dataflow (SDF) graphs. Our approach is based on describing the evolution of actor firing times as a linear time-invariant system in max-plus algebra. Experimental results indicate that our approach is faster than state-of-the-art approaches to throughput analysis ...
Keywords: dataflow, streaming applications, timing analysis, max-plus algebra

10
August 2011 DSD '11: Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Synchronous hardware can be straight forwardly modelled as a function from input and (current) state to an updated state and output. The C?aSH compiler can translate such a transition function, described in a functional language, to synthesisable VHDL. Taking a hardware-oriented viewpoint, components can then be seen as an instantiation ...
Keywords: Functional programming, Hardware description languages, Pipeline processing

11 published by ACM
June 2011 ACM SIGBED Review - Work-in-Progress (WiP) Session of the 2nd International Conference on Cyber Physical Systems: Volume 8 Issue 2, June 2011
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1,   Downloads (12 Months): 13,   Downloads (Overall): 80

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The design of cyber-physical systems requires the use of mixed continuous time and discrete time models. Current modelling tools have problems with time transformations (such as a time delay) or multi-rate systems. We will present a novel approach that implements signals as functions of time, directly corresponding to their mathematical ...

12
September 2010 DSD '10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 10

CλaSH is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. Polymorphism and higher-order functions provide a level of abstraction and generality that allow a circuit designer to describe circuits in a more natural way than possible with the language elements ...

13
September 2010 DSD '10: Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 4

This paper presents an approximate Maximum Common Sub graph (MCS) algorithm, specifically for directed, cyclic graphs representing digital circuits. Because of the application domain, the graphs have nice properties: they are very sparse, have many different labels, and most vertices have only one predecessor. The algorithm iterates over all vertices ...

14
September 2010 IFL'10: Proceedings of the 22nd international conference on Implementation and application of functional languages
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 1

Processor designs specialized for functional languages received very little attention in the past 20 years. The potential for exploiting more parallelism and the developments in hardware technology, ask for renewed investigation of this topic. In this paper, we use ideas from modern processor architectures and the state of the art ...

15
March 2010 DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: European Design and Automation Association
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 3,   Downloads (12 Months): 6,   Downloads (Overall): 98

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Design-time application mapping is limited to a predefined set of applications and a static platform. Resource management at run-time is required to handle future changes in the application set, and to provide some degree of fault tolerance, due to imperfect production processes and wear of materials. This paper concerns resource ...

16 published by ACM
September 2009 Haskell '09: Proceedings of the 2nd ACM SIGPLAN symposium on Haskell
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 8,   Downloads (Overall): 68

Full text available: Mp4Mp4

17
August 2009 DSD '09: Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1


18 published by ACM
January 2009 PEPM '09: Proceedings of the 2009 ACM SIGPLAN workshop on Partial evaluation and program manipulation
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 4,   Downloads (Overall): 107

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Wireless sensor and actuator networks consist of a large number of disparate computing devices that together aim to perform a common tasks. Management of large networks may become difficult, when the individual task of each of the devices is different from others, and memory restrictions prevent the devices from all ...
Keywords: partial evaluation, wireless sensor networks

19 published by ACM
December 2008 MidSens '08: Proceedings of the 3rd international workshop on Middleware for sensor networks
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 4,   Downloads (Overall): 105

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Wireless sensor networks communication protocols and abstractions have remained fairly simple until now, dealing only with payloads the size of individual network packets. A method to transparently communicate variably sized data in a platform-agnostic manner may ease building energyefficient and robust applications. This paper presents a communication abstraction that enables ...
Keywords: memory management, reliable communication, wireless sensor networks, transmission protocol

20
September 2008 DSD '08: Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Developing code for SIMD type hardware architectures is a tedious job. This is caused by the absence of both a coherent methodological framework and a hardware independent tooling. Moreover, the inherently difficult nature of programming dedicated massively parallel embedded processors, complicates the matter. This paper describes a single framework, called ...
Keywords: firmware development, SIMD architectures, executability, functional languages



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