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 Charles Chilton Weems

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Average citations per article3.47
Citation Count205
Publication count59
Publication years1984-2015
Available for download8
Average downloads per article426.13
Downloads (cumulative)3,409
Downloads (12 Months)116
Downloads (6 Weeks)12
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59 results found Export Results: bibtexendnoteacmrefcsv

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1
September 2015
Bibliometrics:
Citation Count: 2

Topics in Parallel and Distributed Computing provides resources and guidance for those learning PDC as well as those teaching students new to the discipline. The pervasiveness of computing devices containing multicore CPUs and GPUs, including home and office PCs, laptops, and mobile devices, is making even common users dependent on ...

2 published by ACM
May 2015 ACM Transactions on Architecture and Code Optimization (TACO): Volume 12 Issue 2, July 2015
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 6,   Downloads (12 Months): 51,   Downloads (Overall): 309

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Current high-performance computer systems utilize a memory hierarchy of on-chip cache, main memory, and secondary storage due to differences in device characteristics. Limiting the amount of main memory causes page swap operations and duplicates data between the main memory and the storage device. The characteristics of next-generation memory, such as ...
Keywords: Emerging technologies, memory control and access, virtual memory, mass storage

3
August 2013 Microprocessors & Microsystems: Volume 37 Issue 6-7, August, 2013
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 2

As DRAM-based main memory becomes a dominant factor in the energy consumption and cost of any computer system, new non-volatile memory technologies have been proposed to replace DRAMs. For example, PRAM is emerged as a leading alternative for main memory technology. However, the access latency of PRAM is significantly slower ...
Keywords: Component, DRAM, Non-volatile memory, Main memory, Phase-change RAM, Cache memory

4
May 2013 IPDPSW '13: Proceedings of the 2013 IEEE 27th International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Multiprocessing modular exponentiation has a variety of uses, including cryptography, prime testing and computational number theory. It is also a very costly operation to compute. GPU parallelism can be used to accelerate these computations, but to use the GPU efficiently, a problem must involve a significant number of simultaneous exponentiation ...
Keywords: modular exponentiation, RSA, PTX code generation, GPU

5
January 2012 IEEE Transactions on Computers: Volume 61 Issue 1, January 2012
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 9

To enhance performance of flash memory-based solid state disk (SSD), large logically chained blocks can be assembled by binding adjacent flash blocks across several flash memory chips. However, flash memory does not allow in-place overwriting and thus the operations that merge writes on these blocks suffer a visible decrease in ...
Keywords: Disk access pattern, flash translation layer, NAND flash memory, secondary storage, solid state disk.

6
December 2011 HIPC '11: Proceedings of the 2011 18th International Conference on High Performance Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

We report an algorithm for division of a multi-precision integer by a single-precision value using a graphics processing unit (GPU). Our algorithm combines a parallel version of Jebelean's exact division algorithm with a left-to-right algorithm for computing the borrow chain, to relax the requirement of exactness. We also employ Takahashi's ...

7
May 2011 IPDPSW '11: Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

We have improved our prior implementation of Strassen's algorithm for high performance multiplication of very large integers on a general purpose graphics processor (GPU). A combination of algorithmic and implementation optimizations result in a factor of 2.3 speed improvement over our previous work, running on an NVIDIA 295. We have ...

8 published by ACM
March 2011 SIGCSE '11: Proceedings of the 42nd ACM technical symposium on Computer science education
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 2,   Downloads (12 Months): 15,   Downloads (Overall): 118

Full text available: PDFPDF
Keywords: education, learning outcomes, parallel and distributed computing, undergraduate curriculum, Bloom's classification

9
February 2011 Microprocessors & Microsystems: Volume 35 Issue 1, February, 2011
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 5

This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, ...
Keywords: Hybrid flash, Solid state disk, Flash translation layer, Multi bank memory

10
November 2010 Journal of Parallel and Distributed Computing: Volume 70 Issue 11, November, 2010
Publisher: Academic Press, Inc.
Bibliometrics:
Citation Count: 1

In order to guarantee both performance and programmability demands in 3D graphics applications, vector and multithreaded SIMD architectures have been employed in recent graphics processing units. This paper introduces a novel instruction-systolic array architecture, which transfers an instruction stream in a pipelined fashion to efficiently share the expensive functional resources ...
Keywords: Instructoin systolic, Programmable GPU, SIMD, Pipelined management

11
November 2009 IEEE Transactions on Multimedia: Volume 11 Issue 7, November 2009
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

For ubiquitous computing environments, an important parameter is whether all the components in the specific environment can connect with one another. Given this capability, we can share various kinds of content across mobile terminals. This paper introduces an effective scheme to manage multimedia sharing based on specially designed profiles and ...
Keywords: P2P network, Community computing, personal space, ubiquitous computing, community computing, user/community profile

12 published by ACM
August 2009 ICHIT '09: Proceedings of the 2009 International Conference on Hybrid Information Technology
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 5,   Downloads (Overall): 181

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We present a fast motion estimation engine for the Unsymmetrical cross Multi-Hexagon-Grid-Search (UMHexagonS) algorithm used in H.264 video encoding. The architecture uses arrays of subtracting elements to maximize parallelism among search points on vertical or horizontal lines, and reduces sum of absolute differences (SAD) calculations. Performance is measured in terms ...
Keywords: parallel accelerator, H.264, UMHexagonS, motion estimation engine, video encoding

13
December 2008 Computer Languages, Systems and Structures: Volume 34 Issue 4, December, 2008
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 0

We introduce CASL, the CoGenT Architecture Specification Language, a mixed behavioral-structure architecture description language designed to facilitate fast-prototyping and tool generation for computer architectures with deep pipelines and complicated timing. We motivate a number of CASL features using examples drawn from modeling the IBM Cell Broadband Engine, including implicit connection ...
Keywords: Architecture, Simulation, ADL, Pipeline

14
June 2008 Computer Communications: Volume 31 Issue 9, June, 2008
Publisher: Elsevier Science Publishers B. V.
Bibliometrics:
Citation Count: 1

When a ubiquitous computing environment is based on seamless connectivity, intelligent network management among heterogeneous network interfaces, called vertical handoff (VHO), is required. However, conventional VHO schemes are based only on network information, and do not address service management for seamless service execution. This paper thus proposes a middleware architecture ...
Keywords: Seamless connectivity, Vertical handoff, Application profile, Context-aware processing

15
June 2005 International Journal of Parallel Programming - Special issue: The next generation software program: Volume 33 Issue 2, June 2005
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 3

It is currently difficult fully to understand the performance of a modern dynamic programming language system, such as Java. One must observe execution in the context of specific architectures in order to evaluate the effects of optimizations. To do this we require simulators and compiler back-ends for a wide variety ...
Keywords: instruction set architecture, simulator, language design, compiler, machine description

16
August 2003 The Journal of Supercomputing: Volume 26 Issue 1, August 2003
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 0

The performance of software on modern architectures has grown more and more difficult to predict and analyze, as modern microprocessors have grown more complex. The execution of a program now entails the complex interaction of code, compiler and processor architecture. The current generation of microprocessors is optimized to an existing ...
Keywords: application, data mining, micro-architecture, simulation, tuning, monitoring, performance

17 published by ACM
May 2003 ISCA '03: Proceedings of the 30th annual international symposium on Computer architecture
Publisher: ACM
Bibliometrics:
Citation Count: 49
Downloads (6 Weeks): 1,   Downloads (12 Months): 14,   Downloads (Overall): 999

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Despite large caches, main-memory access latencies still cause significant performance losses in many applications. Numerous hardware and software prefetching schemes have been proposed to tolerate these latencies. Software prefetching typically provides better prefetch accuracy than hardware, but is limited by prefetch instruction overheads and the compiler's limited ability to schedule ...
Also published in:
May 2003  ACM SIGARCH Computer Architecture News - ISCA 2003: Volume 31 Issue 2, May 2003

18
April 2003 IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

To understand the performance of modern Java systems one must observe execution in the context of specific architectures. It is also important that we make these observations using a compiler that is capable of producing optimizations that are specialized to the target machine. Current architectural simulators, however, provide little or ...

19 published by ACM
November 2002 ACM Transactions on Embedded Computing Systems (TECS): Volume 1 Issue 1, November 2002
Publisher: ACM
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 2,   Downloads (12 Months): 15,   Downloads (Overall): 1,228

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This article presents the design of a simple hardware-controlled, high performance cache system. The design supports fast access time, optimal utilization of temporal and spatial localities adaptive to given applications, and a simple dynamic fetching mechanism with different fetch sizes. Support for dynamically varying the fetch size makes the cache ...
Keywords: media application, dynamic block fetching and cache memory, general application, spatial locality, temporal locality, Memory hierarchy

20
September 2002 PACT '02: Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 40

Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with LRU replacement policies to combine fast access with relatively low miss rates. To improve replacement decisions in set-associative caches, we develop a new set of compiler algorithms that predict which ...



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