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 Mohamed Mostafa Zahran

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Average citations per article2.00
Citation Count38
Publication count19
Publication years1999-2017
Available for download10
Average downloads per article1,879.60
Downloads (cumulative)18,796
Downloads (12 Months)3,225
Downloads (6 Weeks)429
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20 results found Export Results: bibtexendnoteacmrefcsv

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1
March 2019
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 24,   Downloads (12 Months): 30,   Downloads (Overall): 30

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If you look around you will find that all computer systems, from your portable devices to the strongest supercomputers, are heterogeneous in nature. The most obvious heterogeneity is the existence of computing nodes of different capabilities (e.g. multicore, GPUs, FPGAs, ...). But there are also other heterogeneity factors that exist ...

2
June 2017 IEEE Transactions on Parallel and Distributed Systems: Volume 28 Issue 6, June 2017
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

Modern graphical processing units (GPUs) are equipped with general-purpose L1 and L2 caches to reduce the memory bandwidth demand and improve the performance of some irregular general-purpose GPU (GPGPU) applications. However, due to the massive multithreading, GPGPU caches suffer from severe resource contention and low data-sharing which may lead to ...

3 published by ACM
February 2017 Communications of the ACM: Volume 60 Issue 3, March 2017
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 15,   Downloads (12 Months): 172,   Downloads (Overall): 754

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Hardware and software perspectives.

4 published by ACM
December 2016 Queue - Authentication: Volume 14 Issue 6, November-December 2016
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 375,   Downloads (12 Months): 2,873,   Downloads (Overall): 15,185

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Hardware and Software Perspectives

5 published by ACM
February 2015 GPGPU-8: Proceedings of the 8th Workshop on General Purpose Processing using GPUs
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 8,   Downloads (12 Months): 50,   Downloads (Overall): 523

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Recent GPUs are equipped with general-purpose L1 and L2 caches in an attempt to reduce memory bandwidth demand and improve the performance of some irregular GPGPU applications. However, due to the massive multithreading, GPGPU caches suffer from severe resource contention and low data-sharing which may degrade the performance instead. In ...
Keywords: Cache Bypassing, GPGPU, Conflict-avoiding, Cache Management, Warp Throttling

6
February 2012 IEEE Transactions on Information Forensics and Security - Part 2: Volume 7 Issue 1, February 2012
Publisher: IEEE Press
Bibliometrics:
Citation Count: 2

A trusted platform module (TPM) enhances the security of general purpose computer systems by authenticating the platform at boot time. Security can often be compromised due to the presence of vulnerabilities in the trusted software that is executed on the system. Existing TPM architectures do not support runtime integrity checking ...

7 published by ACM
October 2011 STC '11: Proceedings of the sixth ACM workshop on Scalable trusted computing
Publisher: ACM
Bibliometrics:
Citation Count: 11
Downloads (6 Weeks): 3,   Downloads (12 Months): 27,   Downloads (Overall): 179

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In this paper, we propose to use hardware performance counters (HPC) to detect malicious program modifications at load time (static) and at runtime (dynamic). HPC have been used for program characterization and testing, system testing and performance evaluation, and as side channels. We propose to use HPCs for static and ...
Keywords: hardware performance counters, integrity

8
October 2011 ICCD '11: Proceedings of the 2011 IEEE 29th International Conference on Computer Design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

With hundreds of processing units in current state-of-the-art graphics processing units (GPUs), the probability that one or more processing units fail due to permanent faults, during fabrication or post deployment, increases drastically. In our experiments we found that the loss of a single streaming multiprocessor (SM) in an 8-SM GPU ...

9
August 2010 IEEE Transactions on Very Large Scale Integration (VLSI) Systems: Volume 18 Issue 8, August 2010
Publisher: IEEE Educational Activities Department
Bibliometrics:
Citation Count: 1

Simultaneous multithreading (SMT) processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is significantly increased, straining the power budget of the processor. This increases not only the dynamic power consumption, but also the leakage power ...
Keywords: computer architecture, power consumption, prediction methods, Computer architecture

10 published by ACM
June 2010 ACM Transactions on Design Automation of Electronic Systems (TODAES): Volume 15 Issue 3, May 2010
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 7,   Downloads (Overall): 290

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This article addresses the problem of chip-level thermal profile estimation using runtime temperature sensor readings. We address the challenges of: (a) availability of only a few thermal sensors with constrained locations (sensors cannot be placed just anywhere); (b) random chip power density characteristics due to unpredictable workloads and fabrication variability. ...
Keywords: estimation, statistical, Thermal profile, on-chip sensor

11 published by ACM
May 2010 CF '10: Proceedings of the 7th ACM international conference on Computing frontiers
Publisher: ACM
Bibliometrics:
Citation Count: 7
Downloads (6 Weeks): 4,   Downloads (12 Months): 37,   Downloads (Overall): 336

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Cache memories currently treat all blocks as if they were equally important. This assumption of equally important blocks is not always valid. For instance, not all blocks deserve to be in L1 cache. We therefore propose globalized block placement. We present a global placement algorithm for managing blocks in a ...
Keywords: cache memory, memory hierarchy

12 published by ACM
April 2009 ACM SIGOPS Operating Systems Review: Volume 43 Issue 2, April 2009
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 3,   Downloads (Overall): 506

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13 published by ACM
June 2007 ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop: Volume 35 Issue 3, June 2007
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 68

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The papers that follow comprise the proceedings of the first Reconfigurable and Adaptive Architecture Workshop (RAAW 2006) that was held in conjunction with the 39 th International Conference on Microarchitecture in Orlando, Florida.

14
February 2005 INTERACT '05: Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Memory system is one of the main performance-limiting factors in contemporary processors. This is due to the gap between the memory system speed and the processor speed. This results in moving as much memory as possible from off-chip to on-chip. Furthermore, we are on a sustained effort into integrating a ...

15
October 2003 ICCD '03: Proceedings of the 21st International Conference on Computer Design
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

There is a growing interest in the use of speculative multithreading to speed up the execution of a program. In speculative multithreading model, threads are extracted from a sequential program and are speculatively executed in parallel, without violating sequential program semantics. In order to get the best performance from this ...

16 published by ACM
March 2003 ACM SIGARCH Computer Architecture News: Volume 31 Issue 1, March 2003
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 2,   Downloads (Overall): 827

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Advances in integrated circuit technology have led the microprocessor design to more challenging areas by providing a high budget of transistors. The one billion microprocessor is not that far from now. This leads microarchitects to look for efficient ways to make use of this feature. Chip-Multiprocessor (CMP) is one of ...

17
January 2003
Bibliometrics:
Citation Count: 0

As we approach billion-transistor processor chips, the need for a new architecture to make efficient use of the increased transistor budget arises. Many studies have shown that significant amounts of unexploited parallelism exist at different granularities, especially for non-numeric programs that are very difficult to parallelize by compilers. Architectures such ...

18
December 2002 HiPC '02: Proceedings of the 9th International Conference on High Performance Computing
Publisher: Springer-Verlag
Bibliometrics:
Citation Count: 1

There is a growing interest in the use of speculative multithreading to speed up the execution of sequential programs. In this execution model, threads are extracted from sequential code and are speculatively executed in parallel. This makes it possible to use parallel processing to speed up ordinary applications, which are ...

19
April 2002 IPDPS '02: Proceedings of the 16th International Parallel and Distributed Processing Symposium
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Many studies have shown that significant amounts of parallelism exist at different granularities. Execution models such as superscalar and VLIW exploit parallelism from a single thread. Multithreaded processors make a step towards exploiting parallelism from different threads, but are not geared to exploit parallelism at different granularities (fine and medium ...

20
July 1999 GECCO'99: Proceedings of the 1st Annual Conference on Genetic and Evolutionary Computation - Volume 1
Publisher: Morgan Kaufmann Publishers Inc.
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 1

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