1

December 2015
IEEE Transactions on Computers: Volume 64 Issue 12, December 2015

**Publisher:** IEEE Computer Society

Transfer functions are concise mathematical models representing the input/output behavior of a system and are widely used in many areas of engineering including system theory and signal analysis. We develop a framework for the construction of transfer function models for digital networks and demonstrate their application in simulation and implication. ...

2

May 2015
ISMVL '15: Proceedings of the 2015 IEEE 45th International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

This paper introduces a reduction rule for edge-valuedmulti-valued decision diagrams (EVMDDs), which improves the speed of analysis of multi-state systems (MSSs). Most reduction rules for decision diagrams remove redundant nodes, while the introduced rule removes redundant edges in EVMDDs. Since the time to do an analysis in an MSS depends ...

**Keywords**:
Reduction rules for decision diagrams, EVMDDs, edge reduction of EVMDDs, multi-state systems, system analysis based on decision diagrams

3

May 2014
ISMVL '14: Proceedings of the 2014 IEEE 44th International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

Multi-Valued (MV) fault trees can be used to represent a variety of probability distributions characterizing system-related events. Representing MV fault trees in the form of multiple-valued decision diagrams (MDD) provides a means for representing overall system probability distributions and are constructed from structure functions. MDD edges are annotated with component ...

**Keywords**:
Multiple-valued Logic, Multiple-valued Decision Diagram, Fault Tree, MDD, System PRobability, pdf, cdf

4

May 2014
ISMVL '14: Proceedings of the 2014 IEEE 44th International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

In a large system, such as a water, gas, or electrical distribution system, degraded performance due to failures of components can be modeled as a set of discrete states interconnected by edges with weights that represent conditional probabilities. To establish such a model, we compute the conditional probabilities with multi-valued ...

**Keywords**:
multi-state systems with multi-state components, structure functions, system analysis based on decision diagrams, system analysis using conditional probabilities, EVMDDs

5

May 2013
ISMVL '13: Proceedings of the 2013 IEEE 43rd International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

Past methods for computation of the spectrum of a multiple-valued logic network usually rely on first characterizing the network in terms of a switching function, secondly in mapping the function values to complex numbers, and thirdly in performing the computation resulting in the spectrum. More recent approaches use decision diagram ...

**Keywords**:
ternary logic, spectral transfer function, spectral response, netlist, spectrum computation

6

May 2013
ISMVL '13: Proceedings of the 2013 IEEE 43rd International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

A linear algebraic method is developed that allows for logic network justification problems to be solved. The method differs from previous techniques that require learning or solution space search techniques in that all possible justification solutions are determined through a single vector-matrix product calculation. The logic network is represented by ...

**Keywords**:
transfer function, justification, ternary logic, multiple-valued logic

7

May 2013
ISMVL '13: Proceedings of the 2013 IEEE 43rd International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

Ternary switching functions are formulated as transformations over vector spaces resulting in a characterization in the form of a transfer function. Ternary logic constants are modeled as vectors, thus the transfer functions are of the form of matrices that map vectors representing logic network input values to corresponding output vectors. ...

**Keywords**:
transfer function, ternary logic, multiple-valued logic

8

May 2012
ISMVL '12: Proceedings of the 2012 IEEE 42nd International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

We present a brief survey of recent developments in reversible sequential circuits and quantum finite state machines based on both binary and multiple-valued solutions. We then argue the benefits of adapting the asynchronous approach for reversible sequential circuit design. We offer several new reversible implementations of key elements to be ...

**Keywords**:
reversible logic, quantum computing, reversible sequential circuits, reversible asynchronous circuits

9

May 2012
ISMVL '12: Proceedings of the 2012 IEEE 42nd International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

Design for medical system reliability has become an area of increasing importance. Medical system threats, which include system failures as well as malicious attacks, often have interdependent events that can adversely affect system operation. To address these problems, we build upon our previous threat cataloging methodology such that a large ...

**Keywords**:
medical system analysis, threat cataloging, MDD, threat probability analysis

10

May 2012
ASYNC '12: Proceedings of the 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

**Publisher:** IEEE Computer Society

Uncle (Unified NULL Convention Logic Environment) is an end-to-end toolset for creating asynchronous designs using NULL Convention Logic (NCL). Designs are specified in Verilog RTL, with the user responsible for specifying registers, data path elements, and finite state machines for controlling data path sequencing. A commercial synthesis tool is used ...

**Keywords**:
asynchronous, NULL Convention Logic, synthesis, RTL

11

February 2012
SIGCSE '12: Proceedings of the 43rd ACM technical symposium on Computer Science Education

**Publisher:** ACM

**Bibliometrics**:

Citation Count: 0

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In early 2011, the ACM and the IEEE Computer Society (IEEE/CS) created the CE2004 Review Task Force (RTF) and charged it with the task of reviewing and determining the extent to which the document "Curriculum Guidelines for Undergraduate Degree Programs in Computer Engineering," produced 2004 December 12 and known as ...

**Keywords**:
ACM, IEEE computer society, computer engineering, curricular report, education

12

May 2011
ISMVL '11: Proceedings of the 2011 41st IEEE International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

The data structure referred to as quantum multiple-valued decision diagrams (QMDD) is used to efficiently represent the unitary matrices describing reversible and quantum circuits. This paper investigates the conditions that cause skipped variables to appear in the QMDD of some binary and ternary quantum circuits. We have found that a ...

**Keywords**:
quantum computing, unitary matrices, QMDD

13

May 2011
ISMVL '11: Proceedings of the 2011 41st IEEE International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

System security continues to be of increasing importance. To effectively address both natural and intentional threats to large systems, the threats must be cataloged and analyzed. Extremely large and complex systems can have an accordingly large number of threat scenarios. Simply listing the threats and devising countermeasures for each is ...

**Keywords**:
Large System Security, Threat cataloging, MDD

14

May 2010
ISMVL '10: Proceedings of the 2010 40th IEEE International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is based on Field Effect Transistors (FETs) that have different voltage threshold levels. The resulting logic cell library is sufficient to implement all possible quaternary ...

**Keywords**:
quaternary logic, arithmetic logic circuits

15

February 2010

Integrated circuit capacity follows Moore's law, and chips are commonly produced at the time of this writing with over 70 million gates per device. Ensuring correct functional behavior of such large designs before fabrication poses an extremely challenging problem. Formal verification validates the correctness of the implementation of a design ...

16

July 2009
ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors

**Publisher:** IEEE Computer Society

An implementation of a radix-4 approximate squaring circuit is described employing a new operand dual recoding technique. Approximate squaring circuits have numerous applications including use in computer graphics, digital radio modules, implementation of division and function approximation in ALU circuits. The theory of operation of the circuit is described including ...

**Keywords**:
radix-4, squaring, operand dual recoding

17

May 2009
ISMVL '09: Proceedings of the 2009 39th International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

This paper proposes a framework that improves reversible logic synthesis by employing a dynamically determined variable order for quantum multiple-valued decision diagrams (QMDD). We demonstrate our approach through augmentation of the Miller-Maslov-Dueck (MMD) algorithm that processes the complete function specification in lexicographical order with our technique. We represent and minimize ...

**Keywords**:
MVL, reversible logic, quantum logic, reversible logic synthesis, QMDD, reversible MVL synthesis

18

May 2009
ISMVL '09: Proceedings of the 2009 39th International Symposium on Multiple-Valued Logic

**Publisher:** IEEE Computer Society

Multiple Valued Logic (MVL) has been gaining popularity and practical applications. In addition to the standard MVL benefits, quaternary logic offers the benefit of easy interfacing to binary logic due to the fact that the radix 4=22 allows for simple encoding/decoding circuits. Quaternary cells based on the Supplementary Symmetrical Logic ...

**Keywords**:
Quaternary, SUSLOC, Voltage-mode circuit, addition circuit

19

February 2009
IEEE Transactions on Computers: Volume 58 Issue 2, February 2009

**Publisher:** IEEE Computer Society

We present a k-bit encoding of the k-bit binary integers based on a discrete logarithm representation. The representation supports a discrete logarithm number system (DLS) that allows integer multiplication to be reduced to addition and integer exponentiation to be reduced to multiplication. We introduce right-to-left bit serial conversion, deconversion, and ...

**Keywords**:
High-speed arithmetic, arithmetic and logic units, computer arithmetic, discrete logarithm, number encodings, conversions, bit serial, integer power, table lookup., bit serial, arithmetic and logic units, computer arithmetic, conversions, Arithmetic and logic units, Computer arithmetic, High-Speed Arithmetic, High-speed arithmetic, discrete logarithm, integer power, number encodings, table lookup.

20

May 2008
ISMVL '08: Proceedings of the 38th International Symposium on Multiple Valued Logic

**Publisher:** IEEE Computer Society

The mathematical property of inheritance for certain unary fixed point operations has recently been exploited to enable the efficient formulation of arithmetic algorithms and circuits for operations such as the modular multiplicative inverse, exponentiation, and discrete logarithm computation in classical binary logic circuits. This principle has desirable features with regard ...

**Keywords**:
Quantum Logic, Arithmetic Circuits, Multiple-Valued Quantum Gate, Inheritance Principle