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 Giorgos Dimitrakopoulos

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Average citations per article2.05
Citation Count80
Publication count39
Publication years2002-2017
Available for download15
Average downloads per article121.07
Downloads (cumulative)1,816
Downloads (12 Months)279
Downloads (6 Weeks)20
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39 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
June 2017 DAC '17: Proceedings of the 54th Annual Design Automation Conference 2017
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 8,   Downloads (12 Months): 107,   Downloads (Overall): 107

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To reduce clock power, we present a novel timing-driven incremental multi-bit register (MBR) composition methodology for designs that may be rich in MBRs after logic synthesis. It identifies nearby compatible registers that can be merged without degrading timing, and without reducing the "useful clock skew" potential. These registers are merged ...

2 published by ACM
January 2017 AISTECS '17: Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 4,   Downloads (12 Months): 24,   Downloads (Overall): 24

Full text available: PDFPDF
Implementing cost effective congestion control within the Network-on-Chip (NoC) is a major design challenge. Whenever congestion awareness and/or mitigation is desired, architects typically rely on the use of adaptive routing algorithms, which aim to (intelligently) balance the traffic load throughout the NoC. Nevertheless, the hardware cost incurred by such solutions ...
Keywords: multi-core, congestion management, network-on-chip, low-cost architecture

3
November 2016
Bibliometrics:
Citation Count: 0

This book provides a concise and comprehensive overview of vehicular communication technologies. It classifies all relevant standards, protocols and applications, so as to enable the reader to gain a holistic approach towards the subject of vehicular communications. The primary methods are algorithmic processes and simulation results. First, an overview and ...

4
October 2016 IEEE Transactions on Computers: Volume 65 Issue 10, October 2016
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Scalable Network-on-Chip (NoC) architectures should achieve high-throughput and low-latency operation without exceeding the stringent area/energy constraints of modern Systems-on-Chip (SoC), even when operating under a high clock frequency. Such requirements directly impact the NoC routers and interfaces comprising the NoC architecture. This paper focuses on the micro-architecture of NoC routers ...

5 published by ACM
June 2016 ACM Transactions on Architecture and Code Optimization (TACO): Volume 13 Issue 2, June 2016
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 4,   Downloads (12 Months): 74,   Downloads (Overall): 160

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Networks-on-Chip (NoC) are becoming increasingly susceptible to emerging reliability threats. The need to detect and localize the occurrence of faults at runtime is steadily becoming imperative. In this work, we propose NoCAlert , a comprehensive online and real-time fault detection and localization mechanism that demonstrates 0% false negatives within the ...
Keywords: fault detection/diagnosis, fault localization, NoC, Networks-on-chip

6 published by ACM
May 2016 GLSVLSI '16: Proceedings of the 26th edition on Great Lakes Symposium on VLSI
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 23,   Downloads (Overall): 67

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Technology scaling of tiled-based CMPs reduces the physical size of each tile and increases the number of tiles per die. This trend directly impacts the on-chip interconnect; even though the tile population increases, the inter-tile link distances scale down proportionally to the tile dimensions. The decreasing inter-tile wire lengths can ...
Keywords: low power, network on chip, VLSI, dual edge clocking

7
May 2016 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems: Volume 35 Issue 5, May 2016
Publisher: IEEE Press
Bibliometrics:
Citation Count: 0

As multi/many-core architectures evolve, the demands on the network-on-chip (NoC) are amplified. In addition to high performance and physical scalability, the NoC is increasingly required to also provide specialized functionality, such as network virtualization, flow isolation, and quality-of-service. Although traditional architectures supporting virtual channels (VCs) offer the resources for flow ...

8
March 2016 DATE '16: Proceedings of the 2016 Conference on Design, Automation & Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 0,   Downloads (Overall): 3

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Technology scaling, process variations, and/or 3D integration make the design of fully synchronous Systems-on-Chip (SoC) a challenging task. Partitioning the SoC into Globally Asynchronous, Locally Synchronous (GALS) islands -- aka clock domains -- partially alleviates the difficulties in clock distribution. Such partitioning of the SoC is also necessary when supporting ...

9
March 2015 DATE '15: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 1,   Downloads (12 Months): 14,   Downloads (Overall): 102

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The efficiency of modern Networks-on-Chip (NoC) is no longer judged solely by their physical scalability, but also by their ability to deliver high performance, Quality-of-Service (QoS), and flow isolation at the minimum possible cost. Although traditional architectures supporting Virtual Channels (VC) offer the resources for flow partitioning and isolation, an ...

10
March 2015 Design Automation for Embedded Systems: Volume 19 Issue 1-2, March 2015
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 4

As multi-core systems transition to the many-core realm, the pressure on the interconnection network is substantially elevated. The Network-on-Chip (NoC) is expected to undertake the expanding demands of the ever-increasing numbers of processing elements, while--at the same time--technological and application constraints increase the pressure for increased performance and efficiency with ...
Keywords: Optical NoCs, Virtualization, Microarchitecture, Physical integration, Wireless NoCs, Network on chip

11
September 2014 Design Automation for Embedded Systems: Volume 18 Issue 3-4, September 2014
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 0


12
August 2014
Bibliometrics:
Citation Count: 1

This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and ...

13
March 2014 DATE '14: Proceedings of the conference on Design, Automation & Test in Europe
Publisher: European Design and Automation Association
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 2,   Downloads (Overall): 28

Full text available: PDFPDF
Elastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variable-latency computations. At the same time, multithreading increases the utilization of processing units and hides the latency of each operation by time-multiplexing operations of different threads in the datapath. This paper proposes a model to unify ...

14
March 2014 DATE '14: Proceedings of the conference on Design, Automation & Test in Europe
Publisher: European Design and Automation Association
Bibliometrics:
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 4,   Downloads (Overall): 39

Full text available: PDFPDF
The design of scalable Network-on-Chip (NoC) architectures calls for new implementations that achieve high-throughput and low-latency operation, without exceeding the stringent area-energy constraints of modern Systems-on-Chip (SoC). The router's buffer architecture is a critical design aspect that affects both network-wide performance and implementation characteristics. In this paper, we extend Elastic ...

15
October 2013 IEEE Transactions on Computers: Volume 62 Issue 10, October 2013
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

Large systems-on-chip (SoCs) and chip multiprocessors (CMPs), incorporating tens to hundreds of cores, create a significant integration challenge. Interconnecting a huge amount of architectural modules in an efficient manner, calls for scalable solutions that would offer both high throughput and low-latency communication. The switches are the basic building blocks of ...
Keywords: Switches,Multiplexing,Resource management,Vectors,Logic gates,System-on-a-chip,Routing,and logic design,Switch allocation,arbiters,crossbar,interconnection networks

16
March 2013 DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 86

Full text available: PDFPDF
On-chip interconnection networks simplify the increasingly challenging process of integrating multiple functional modules in modern Systems-on-Chip (SoCs). The routers are the heart and backbone of such networks, and their implementation cost (area/power) determines the cost of the whole network. In this paper, we explore the time-multiplexing of a router's output ...

17
August 2012 IEEE Transactions on Very Large Scale Integration (VLSI) Systems: Volume 20 Issue 8, August 2012
Publisher: IEEE Educational Activities Department
Bibliometrics:
Citation Count: 3

High-end embedded processors demand complex on-chip cache hierarchies satisfying several contradicting design requirements such as high-performance operation and low energy consumption. This paper introduces light-power (LP) nonuniform cache architecture (NUCA), a tiled-cache addressing both goals. LP-NUCA places a group of small and low-latency tiles between the L1 and the last ...
Keywords: cache organization, VLSI, interconnection networks, low-power design, nonuniform cache architecture (NUCA), network-on-chip

18
June 2012 IEEE Transactions on Intelligent Transportation Systems: Volume 13 Issue 2, June 2012
Publisher: IEEE Press
Bibliometrics:
Citation Count: 1

Information and communication technologies (ICTs) have long been attracting research interest, which is reflected in the design and development of powerful and complex network infrastructures, advanced applications/services, efficient power management, and extensions in the business model. A field of applications where ICTs find prosperous ground is transportation, in the sense ...

19
March 2012 DATE '12: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: EDA Consortium
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 9,   Downloads (Overall): 84

Full text available: PDFPDF
On-chip interconnection networks simplify the integration of complex system-on-chips. The switches are the basic building blocks of such networks and their design critically affects the performance of the whole system. The transfer of data between the inputs and the outputs of the switch is performed by the crossbar, whose active ...

20
February 2012 IEEE Transactions on Computers: Volume 61 Issue 2, February 2012
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

Two architectures for modulo 2^n+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2^n+1 addition. This sparse approach is enabled by the introduction of the inverted circular idempotency property of the ...
Keywords: Modulo arithmetic, residue number system (RNS), parallel-prefix carry computation, computer arithmetic, VLSI.



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