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 Stephan Held

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Average citations per article3.50
Citation Count49
Publication count14
Publication years2003-2017
Available for download9
Average downloads per article155.00
Downloads (cumulative)1,395
Downloads (12 Months)132
Downloads (6 Weeks)29
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1 published by ACM
December 2017 ACM Transactions on Algorithms (TALG): Volume 14 Issue 1, January 2018
Publisher: ACM
Citation Count: 0
Downloads (6 Weeks): 23,   Downloads (12 Months): 23,   Downloads (Overall): 23

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We consider the problem of constructing fast and small binary adder circuits. Among widely used adders, the Kogge-Stone adder is often considered the fastest, because it computes the carry bits for two n -bit numbers (where n is a power of two) with a depth of 2 log 2 n ...
Keywords: depth, circuit, Binary addition, parallel, size, combinational complexity, fan-out

February 2017 Computational Geometry: Theory and Applications: Volume 61 Issue C, February 2017
Publisher: Elsevier Science Publishers B. V.
Citation Count: 0

Given a set P of terminals in the plane and a partition of P into k subsets P 1 , ź , P k , a two-level rectilinear Steiner tree consists of a rectilinear Steiner tree T i connecting the terminals in each set P i ( i = 1 ...
Keywords: Approximation algorithms, VLSI design, Steiner trees

January 2017 Algorithmica: Volume 77 Issue 1, January 2017
Publisher: Springer-Verlag New York, Inc.
Citation Count: 1

We consider the problem of constructing fast and small parallel prefix adders for non-uniform input arrival times. In modern computer chips, adders with up to hundreds of inputs occur frequently, and they are often embedded into more complex circuits, e.g. multipliers, leading to instance-specific non-uniform input arrival times. Most previous ...
Keywords: Addition, 68Q25, Circuit, Parallel prefix problem, Delay, Prefix adder, 65Y04, Non-uniform input arrival times

November 2015 ICCAD '15: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design
Publisher: IEEE Press
Citation Count: 1
Downloads (6 Weeks): 2,   Downloads (12 Months): 18,   Downloads (Overall): 95

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We show how to incorporate global static timing constraints into global routing. Our approach is based on the min-max resource sharing model that proved successful for global routing in theory and practice. Static timing constraints are modeled by a linear number of additional resources and customers. The algorithm dynamically adjusts ...
Keywords: timing constraints, wire synthesis, global routing

5 published by ACM
June 2015 DAC '15: Proceedings of the 52nd Annual Design Automation Conference
Publisher: ACM
Citation Count: 4
Downloads (6 Weeks): 1,   Downloads (12 Months): 29,   Downloads (Overall): 188

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We present local search algorithms for timing-driven placement optimization. They find local slack optima for cells under arbitrary delay models and can be applied late in the design flow. The key ingredients are an implicit path straightening and a clustering of neighboring cells. Cell clusters are moved jointly to speed ...
Keywords: accurate delay models, local search, timing-driven placement

6 published by ACM
June 2014 DAC '14: Proceedings of the 51st Annual Design Automation Conference
Publisher: ACM
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 19,   Downloads (Overall): 157

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We present an algorithm which permutes latch positions and sizes within a clock cluster to maximize the worst slack. It preserves the clock footprint and routing, and can therefore be applied late in the design flow after clock network design. The algorithm realizes the best achievable worst slack based on ...
Keywords: Clock network, latch clustering, latch planning

7 published by ACM
March 2014 ISPD '14: Proceedings of the 2014 on International symposium on physical design
Publisher: ACM
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 16,   Downloads (Overall): 145

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We study the minimum rectilinear Steiner tree problem in the presence of obstacles. Traversing obstacles is not strictly forbidden, but the total length of each connected component in the intersection of the tree with the interior of the blocked area is bounded by a constant. This problem is motivated by ...
Keywords: steiner tree, obstacle-aware, bu ffering, interconnect planning

March 2013 IPCO'13: Proceedings of the 16th international conference on Integer Programming and Combinatorial Optimization
Publisher: Springer-Verlag
Citation Count: 3

We consider the problem of constructing a Steiner arborescence broadcasting a signal from a root r to a set T of sinks in a metric space, with out-degrees of Steiner vertices restricted to 2. The arborescence must obey delay bounds for each r - t -path ( t ∈ T ...

June 2011 IPCO'11: Proceedings of the 15th international conference on Integer programming and combinatoral optimization
Publisher: Springer-Verlag
Citation Count: 2

The best known method for determining lower bounds on the vertex coloring number of a graph is the linear-programming columngeneration technique first employed by Mehrotra and Trick in 1996. We present an implementation of the method that provides numerically safe results, independent of the floating-point accuracy of linear-programming software. Our ...
Keywords: column generation, graph coloring, maximum-weight stable set, safe computations, fractional chromatic number

November 2010 Information Processing Letters: Volume 110 Issue 24, November, 2010
Publisher: Elsevier North-Holland, Inc.
Citation Count: 4

A tree-like substructure on a computer chip whose task is to carry a signal from a source circuit to possibly many sink circuits and which consists only of wires and so-called repeater circuits is called a repeater tree. We present a mathematical formulation of the optimization problems related to the ...
Keywords: VLSI design, Analysis of algorithms, Minimum spanning tree, Repeater tree, Interconnection networks, Steiner tree

April 2009 DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe
Publisher: European Design and Automation Association
Citation Count: 4
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 86

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Today, many chips are designed with predefined discrete cell libraries. In this paper we present a new fast gate sizing algorithm that works natively with discrete cell choices and realistic timing models. The approach iteratively assigns signal slew targets to all source pins of the chip and chooses discrete layouts ...

12 published by ACM
March 2009 ISPD '09: Proceedings of the 2009 international symposium on Physical design
Publisher: ACM
Citation Count: 2
Downloads (6 Weeks): 0,   Downloads (12 Months): 2,   Downloads (Overall): 137

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We present a very fast algorithm for buffering repeater trees. We scan a given preliminary topology in a bottom-up fashion and insert buffers and inverters, respecting the parities of the sinks. Information obtained by preprocessing allows for very fast decisions. To bound the number of shielding repeaters, they are only ...
Keywords: interconnect buffering, physical design, timing closure, repeater insertion, repeater tree

13 published by ACM
April 2006 ISPD '06: Proceedings of the 2006 international symposium on Physical design
Publisher: ACM
Citation Count: 7
Downloads (6 Weeks): 2,   Downloads (12 Months): 5,   Downloads (Overall): 264

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We present a very fast algorithm for topology generation of repeater trees. Based on the criticality of the individual sinks, which is estimated taking their required signal arrival times and their distance from the root of the repeater tree into account, this topology connects very critical sinks in such a ...
Keywords: tree topology, inverter tree, repeater tree, buffering, rectilinear Steiner tree

November 2003 ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Publisher: IEEE Computer Society
Citation Count: 19
Downloads (6 Weeks): 0,   Downloads (12 Months): 9,   Downloads (Overall): 289

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In this paper we present a new method for clock schedulingand clocktree construction that improves the performance ofhigh-end ASICs significantly.First, we compute a clock schedule that yields the optimumcycle time and the best possible clock distribution with respectto early and late mode; in particular the number of criticaltests is minimized. ...

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