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 Scott Alan Hauck

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Bibliometrics: publication history
Average citations per article17.43
Citation Count1,429
Publication count82
Publication years1992-2016
Available for download31
Average downloads per article829.03
Downloads (cumulative)25,700
Downloads (12 Months)1,113
Downloads (6 Weeks)91
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82 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
October 2016 Communications of the ACM: Volume 59 Issue 11, November 2016
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 10,   Downloads (12 Months): 128,   Downloads (Overall): 968

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Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we designed and built a composable, reconfigurable hardware fabric based on field programmable gate arrays (FPGA). Each ...

2
May 2015 FCCM '15: Proceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Coarse Grained Reconfigurable Arrays (CGRAs) offer improved energy efficiency and performance over conventional architectures. However, modulo counter based control of these devices limits efficiency for applications with multiple execution modes. This work presents a new type of architecture that adds support for branching control flow to CGRAs. The pipelined program ...
Keywords: CGRA, scheduling, software pipelining

3
May 2015 FCCM '15: Proceedings of the 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Data compression techniques have been the subject of intense study over the past several decades due to exponential increases in the quantity of data stored and transmitted by computer systems. Compression algorithms are traditionally forced to make tradeoffs between throughput and compression quality (the ratio of original file size to ...
Keywords: FPGA, data compression, LZ77, Huffman encoding, hardware accelerator, Xpress, high throughput

4
June 2014 ISCA '14: Proceeding of the 41st annual international symposium on Computer architecuture
Publisher: IEEE Press
Bibliometrics:
Citation Count: 184
Downloads (6 Weeks): 29,   Downloads (12 Months): 482,   Downloads (Overall): 1,682

Full text available: PDFPDF
Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurablefabric to accelerate portions of large-scale software services. Each instantiation ...
Also published in:
October 2014  ACM SIGARCH Computer Architecture News - ISCA '14: Volume 42 Issue 3, June 2014

5
May 2014 FCCM '14: Proceedings of the 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Data compression is crucial in large-scale storage servers to save both storage and network bandwidth, but it suffers from high computational cost. In this work, we present a high throughput FPGA based compressor as a PCIe accelerator to achieve CPU resource saving and high power efficiency. The proposed compressor is ...
Keywords: FPGA, data compression, LZ77, Huffman encoding, hardware accelerator, Xpress, high throughput

6 published by ACM
February 2013 FPGA '13: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 2,   Downloads (12 Months): 7,   Downloads (Overall): 215

Full text available: PDFPDF
Over the last decade, the number of known biologically important non-coding RNAs (ncRNAs) has increased by orders of magnitude. The function performed by a specific ncRNA is partially determined by its structure, defined by which nucleotides of the molecule form pairs. These correlations may span large and variable distances in ...
Keywords: CYK, FPGA, ncRNA, reconfigurable computing, viterbi

7
July 2012 SAAHPC '12: Proceedings of the 2012 Symposium on Application Accelerators in High Performance Computing
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 0

Genomics computing is indispensable in basic medical research as well as in practical applications such as disease prevention, pharmaceutical development, and criminal forensics. DNA sequencing, assembly and analysis are key components of genomics computing. Coupled with the increased use of computation for both synthesis and analysis of data in genomics ...
Keywords: FPGAs, configurable computing, bioinformatics

8
April 2012 FCCM '12: Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 15

Bioinformatics is an emerging field with seemingly limitless possibilities for advances in numerous areas of research and applications. We propose a scalable FPGA-based solution to the short read mapping problem in DNA sequencing, which greatly accelerates the task of aligning short length reads to a known reference genome. We compare ...
Keywords: bioinformatics, short reads, mapping, nextgeneration sequencing, FPGA

9 published by ACM
February 2012 FPGA '12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Publisher: ACM
Bibliometrics:
Citation Count: 1

Coarse Grained Reconfigurable Arrays (CGRAs) are a promising class of architectures for accelerating applications using a large number of parallel execution units for high throughput. While they are typically very efficient for a single task, all functional units are required to perform in lock step; this makes some classes of ...
Keywords: mppa, architecture, cgra

10 published by ACM
December 2011 ACM Transactions on Reconfigurable Technology and Systems (TRETS): Volume 4 Issue 4, December 2011
Publisher: ACM
Bibliometrics:
Citation Count: 16
Downloads (6 Weeks): 5,   Downloads (12 Months): 86,   Downloads (Overall): 891

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Fine-grain reconfigurable devices suffer from the time needed to load the configuration bitstream. Even for small bitstreams in partially reconfigurable FPGAs this time cannot be neglected. In this article we survey the performance of the factors that contribute to the reconfiguration speed. Then, we study an FPGA-based system architecture and ...
Keywords: partial reconfiguration, reconfiguration time, Reconfigurable computing, field programmable gate arrays

11 published by ACM
June 2011 EXADAPT '11: Proceedings of the 1st International Workshop on Adaptive Self-Tuning Computing Systems for the Exaflop Era
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 1,   Downloads (Overall): 96

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It is hard to optimize applications for coprocessor accelerator architectures, like FPGAs and GPUs, because application parameters must be tuned carefully to the size of the target architecture. Moreover, some combinations of parameters simply do not work, because they lead to overuse of a constrained resource. Applying auto-tuning---the use of ...
Keywords: auto-tuning, optimization, accelerator architectures, probabilistic

12
May 2011 FCCM '11: Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

Coarse Grained Reconfigurable Arrays (CGRAs) are typically very efficient for a single task. However all functional units are required to perform in lock step, wasting resources and making complex programming flows difficult. Massively Parallel Processor Arrays (MPPAs) excel at executing unrelated tasks simultaneously, but limit the amount of resources dedicated ...
Keywords: CGRA, MPPA, flow control, inteconnect

13
May 2011 FCCM '11: Proceedings of the 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

XIn this paper, we use an FPGA platform and a high level synthesis tool, called Impulse C, to speedup a statistical Line Of Reaction (LOR) estimation for a high-resolution Positron Emission Tomography (PET) scanner. The estimation algorithm provides a significant improvement over conventional methods, but the execution time is too ...
Keywords: FPGA, High Level Synthesis, LOR estimation, PET scanner

14 published by ACM
February 2011 FPGA '11: Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 1,   Downloads (12 Months): 3,   Downloads (Overall): 240

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Functional units provide the backbone of any spatial accelerator by providing the computing resources. The desire for having rich and expensive functional units is in tension with producing a regular and energy-efficient computing fabric. This paper explores the design trade-off between complex, universal functional units and simpler, limited functional units. ...
Keywords: architecture, cgra, energy-efficiency, functional units

15
August 2010 FPL '10: Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Efficient storage in spatial processors is increasingly important as such devices get larger and support more concurrent operations. Unlike sequential processors that rely heavily on centralized storage, e.g. register files and embedded memories, spatial processors require many small storage structures to efficiently manage values that are distributed throughout the processor's ...
Keywords: CGRA, energy-efficiency, storage, architecture

16
August 2010 FPL '10: Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms for building logically larger memories, it often requires developer intervention on word-oriented devices like Massively Parallel Processor Arrays (MPPAs). We examine building larger ...
Keywords: MPPA, memory, pipelining

17
May 2010 FCCM '10: Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 4

While traditional methods of designing FPGA applications have relied on schematics or HDL, much interest has been shown in C-to-FPGA tool flows that allow users to design FPGA hardware in C. We evaluate a C-to-FPGA tool flow (Impulse C) by analyzing the performance of three independent implementations of the Computed ...
Keywords: Impulse C, FPGA, CT Scan, Tomographic Reconstruction

18 published by ACM
February 2009 FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 6,   Downloads (12 Months): 12,   Downloads (Overall): 433

Full text available: PDFPDF
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for positron emission tomography (PET) scanner. Our ...
Keywords: fpga, localization, positron emission tomography, timing

19 published by ACM
February 2009 FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Publisher: ACM
Bibliometrics:
Citation Count: 20
Downloads (6 Weeks): 5,   Downloads (12 Months): 45,   Downloads (Overall): 564

Full text available: PDFPDF
In this paper we present SPR, a new architecture-adaptive mapping tool for use with Coarse-Grained Reconfigurable Architectures (CGRAs). It combines a VLIW style scheduler and FPGA style placement and pipelined routing algorithms with novel mechanisms for integrating and adapting the algorithms to CGRAs. We introduce a latency padding technique that ...
Keywords: clustering, modulo graph, pathfinder, placement, routing, scheduling, spr, static sharing

20 published by ACM
June 2008 DAC '08: Proceedings of the 45th annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 148

Full text available: PDFPDF
FPGA application developers often use pipelining, C-slowing and retiming to improve the performance of their designs. Unfortunately, registered netlists present a fundamentally different problem to CAD tools, potentially limiting the benefit of these techniques. In this paper we discuss some of the inherent issues pipelined netlists pose to existing timing-driven ...
Keywords: FPGA, pipelined, placement, simulated annealing, timing-driven



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