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 William Read Bush

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Average citations per article2.86
Citation Count20
Publication count7
Publication years1986-1992
Available for download3
Average downloads per article285.00
Downloads (cumulative)855
Downloads (12 Months)22
Downloads (6 Weeks)12
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January 1992
Citation Count: 0

A general principle of design is to optimize for common cases. Within the context of global requirements and constraints, improving the performance of commonly occurring cases often improves the overall performance of a complete design. This dissertation applies this principle to the automated synthesis of microprocessor implementations from behavioral, program-like ...
Keywords: automated synthesis

2 published by ACM
May 1990 ACM SIGARCH Computer Architecture News - Special Issue: Proceedings of the 17th annual international symposium on Computer Architecture: Volume 18 Issue 2SI, June 1990
Publisher: ACM
Citation Count: 13
Downloads (6 Weeks): 1,   Downloads (12 Months): 5,   Downloads (Overall): 312

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Most Prolog machines have been based on specialized architectures. Our goal is to start with a general purpose architecture and determine a minimal set of extensions for high performance Prolog execution. We have developed both the architecture and optimizing compiler simultaneously, drawing on results of previous implementations. We find that ...
Also published in:
May 1990  ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture

December 1988
Citation Count: 0

The Advanced Silicon Compiler in Prolog (ASP) is a full-range hardware synthesis system based on Prolog. It produces VLSI masks from instruction set architecture specifications written in Prolog. The system is composed of several hierarchical components that span behavioral, circuit, and geometric synthesis. This report describes the prototype ASP system ...

4 published by ACM
October 1987 ACM SIGARCH Computer Architecture News: Volume 15 Issue 5, Oct. 1987
Publisher: ACM
Citation Count: 6
Downloads (6 Weeks): 7,   Downloads (12 Months): 9,   Downloads (Overall): 382

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The Smalltalk On A RISC project at U. C. Berkeley proves that a high-level object-oriented language can attain high performance on a modified reduced instruction set architecture. The single most important optimization is the removal of a layer of interpretation, compiling the bytecoded virtual machine instructions into low-level, register-based, hardware ...
Also published in:
October 1987  ACM SIGOPS Operating Systems Review: Volume 21 Issue 4, Oct. 1987 October 1987  ACM SIGPLAN Notices: Volume 22 Issue 10, Oct. 1987 October 1987  ASPLOS II: Proceedings of the second international conference on Architectual support for programming languages and operating systems

5 published by ACM
March 1987 ACM SIGARCH Computer Architecture News: Volume 15 Issue 1, March 1987
Publisher: ACM
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 3,   Downloads (Overall): 137

Full text available: PDFPDF

January 1987
Citation Count: 0

The Topolog module generator is the major circuit-design component of the ASP silicon compiler. Topolog is an attempt to determine the utility of Prolog specifically and logic programming generally for the programming of solutions to large-scale VLSI circuit design problems. We have verified that Prolog''s clause-based programming style permits easy ...

June 1986
Citation Count: 0

The SOAR (Smalltalk ON A RISC) project at Berkeley has developed a RISC-style processor designed to execute the Smalltalk-80 language efficiently. This document describes the translator that converts Smalltalk bytecodes into SOAR instructions. Experience with the translator that converts Smalltalk justifies early SOAR assumptions and decisions.

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