Trevor Nigel Mudge
Trevor Nigel Mudge

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Bibliometrics: publication history
Average citations per article23.37
Citation Count4,932
Publication count211
Publication years1977-2016
Available for download133
Average downloads per article530.48
Downloads (cumulative)70,554
Downloads (12 Months)1,842
Downloads (6 Weeks)142
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211 results found Export Results: bibtexendnoteacmrefcsv

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1
December 2016 IEEE Journal on Selected Areas in Communications: Volume 34 Issue 12, December 2016
Publisher: IEEE Press
Bibliometrics:
Citation Count: 1

This paper presents an energy-autonomous wireless communication system for ultra-small Internet-of-Things (IoT) platforms. In the proposed system, all necessary components, including the battery, energy-harvesting solar cells, and the RF antenna, are fully integrated within a millimeter-scale form factor. Designing an energy-optimized wireless communication system for such a miniaturized platform is ...

2
December 2016 IEEE Transactions on Computers: Volume 65 Issue 12, December 2016
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 1

Most server-grade systems provide Chipkill-Correct error protection at the expense of power and performance. In this paper we present a low overhead solution to improving the reliability of commodity DRAM systems with no change in the existing memory architecture. Specifically, we propose five erasure and error correction (E-ECC) schemes that ...

3 published by ACM
June 2016 DAC '16: Proceedings of the 53rd Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 6,   Downloads (12 Months): 55,   Downloads (Overall): 321

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In recent years, operating at near-threshold supply voltages has been proposed to improve energy efficiency in circuits, yet decreased efficacy of dynamic voltage scaling has been observed in recent planar technologies. However, foundries have introduced a shift from planar to FinFET fabrication processes. In this paper, we study 7nm FinFET's ...

4 published by ACM
March 2015 Communications of the ACM: Volume 58 Issue 4, April 2015
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 55,   Downloads (Overall): 964

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5 published by ACM
March 2015 ASPLOS '15: Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems
Publisher: ACM
Bibliometrics:
Citation Count: 27
Downloads (6 Weeks): 19,   Downloads (12 Months): 190,   Downloads (Overall): 1,014

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As user demand scales for intelligent personal assistants (IPAs) such as Apple's Siri, Google's Google Now, and Microsoft's Cortana, we are approaching the computational limits of current datacenter architectures. It is an open question how future server architectures should evolve to enable this emerging class of applications, and the lack ...
Keywords: datacenters, emerging workloads, intelligent personal assistants, warehouse scale computers
Also published in:
May 2015  ACM SIGPLAN Notices - ASPLOS '15: Volume 50 Issue 4, April 2015 May 2015  ACM SIGARCH Computer Architecture News - ASPLOS'15: Volume 43 Issue 1, March 2015

6
January 2015 Journal of Signal Processing Systems: Volume 78 Issue 1, January 2015
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 1

Base stations have been built from ASICs, DSP processors, or FPGAs. This paper studies the feasibility of building wireless base stations from commercial graphics processing units (GPUs). GPUs are attractive because they are widely used massively parallel devices that can be programmed in a high level language. Base station workloads ...
Keywords: Graphics processing unit, Multi-GPU system, Power efficient, Baseband processing, LTE base station

7
December 2014 MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 5
Downloads (6 Weeks): 0,   Downloads (12 Months): 6,   Downloads (Overall): 66

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This paper proposes a novel 3D switch, called 'Hi-Rise', that employs high-radix switches to efficiently route data across multiple stacked layers of dies. The proposed interconnect is hierarchical and composed of two switches per silicon layer and a set of dedicated layer to layer channels. However, a hierarchical 3D switch ...
Keywords: Arbitration, High-Radix Switch, 3D Integration

8
September 2014 Journal of Signal Processing Systems: Volume 76 Issue 3, September 2014
Publisher: Kluwer Academic Publishers
Bibliometrics:
Citation Count: 0

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can ...
Keywords: ECC, MLC NAND Flash, Data refresh, Data retention error, Program interferences error

9 published by ACM
August 2014 ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 9,   Downloads (Overall): 117

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A memory rename table for improved performance, reduced complexity, and reduced energy consumption is proposed and evaluated. It gives an average 8.7% speedup and 7.9% reduction in core and cache energy. The evaluation employs a simulation model for an out-of-order core, similar to the ARM Cortex A15, and McPAT for ...
Keywords: energy-efficiency, load store unit, memory system

10 published by ACM
June 2014 ACM International Conference on Supercomputing 25th Anniversary Volume
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 1,   Downloads (12 Months): 7,   Downloads (Overall): 76

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The paper introduces and evaluates a technique, referred to as runahead, that prefetches instructions and data into the L1 caches on cache misses. The results of the experiments reported in the paper show that the CPI of a simple in-order pipeline could be reduced by 30%. The principle advantage of ...
Keywords: prefetching, runahead, speculation

11 published by ACM
June 2014 DAC '14: Proceedings of the 51st Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 0,   Downloads (12 Months): 2,   Downloads (Overall): 86

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Separable allocators in on-chip routers perform switch allocation in two stages that often make uncoordinated decisions resulting in sub-optimal switch allocation. We propose Virtual Input Crossbars (VIX), where more than one virtual channel (VC) of an input port is connected to the crossbar. VIX improves switch allocation by allowing more ...
Keywords: network-on-chip, throughput, switch-allocation

12 published by ACM
June 2014 DAC '14: Proceedings of the 51st Annual Design Automation Conference
Publisher: ACM
Bibliometrics:
Citation Count: 0
Downloads (6 Weeks): 0,   Downloads (12 Months): 4,   Downloads (Overall): 94

Full text available: PDFPDF
Communication in multi-processor systems-on-chip requires guaranteed throughput and latency. If the network is unaware of ongoing communication patterns, applications may not receive their necessary bandwidth or may suffer high network latencies. Many techniques have been proposed to provide quality-of-service (QoS) in the network by regulating network traffic; however, as network ...
Keywords: network-on-chip, quality-of-service

13 published by ACM
February 2014 ASPLOS '14: Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Publisher: ACM
Bibliometrics:
Citation Count: 14
Downloads (6 Weeks): 2,   Downloads (12 Months): 22,   Downloads (Overall): 579

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Key-value stores, such as Memcached, have been used to scale web services since the beginning of the Web 2.0 era. Data center real estate is expensive, and several industry experts we have spoken to have suggested that a significant portion of their data center space is devoted to key value ...
Keywords: 3d integration, data centers, key-value stores, physical density, scale-out systems
Also published in:
April 2014  ACM SIGPLAN Notices - ASPLOS '14: Volume 49 Issue 4, April 2014 April 2014  ACM SIGARCH Computer Architecture News - ASPLOS '14: Volume 42 Issue 1, March 2014

14 published by ACM
November 2013 SC '13: Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Publisher: ACM
Bibliometrics:
Citation Count: 13
Downloads (6 Weeks): 0,   Downloads (12 Months): 13,   Downloads (Overall): 520

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The power target for exascale supercomputing is 20MW, with about 30% budgeted for the memory subsystem. Commodity DRAMs will not satisfy this requirement. Additionally, the large number of memory chips (>10M) required will result in crippling failure rates. Although specialized DRAM memories have been reorganized to reduce power through 3D-stacking ...

15 published by ACM
November 2013 Communications of the ACM: Volume 56 Issue 11, November 2013
Publisher: ACM
Bibliometrics:
Citation Count: 4
Downloads (6 Weeks): 1,   Downloads (12 Months): 61,   Downloads (Overall): 1,040

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Process scaling has resulted in an exponential increase of the number of transistors available to designers. Meanwhile, global interconnect has not scaled nearly as well, because global wires scale only in one dimension instead of two, resulting in fewer, high-resistance routing tracks. This paper evaluates the use of three-dimensional (3D) ...

16
September 2013 IEEE Micro: Volume 33 Issue 5, September 2013
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 1

Supply-voltage scaling has stagnated in recent technology nodes, leading to so-called dark silicon. To increase overall chip multiprocessor (CMP) performance, it is necessary to improve the energy efficiency of individual tasks so that more tasks can be executed simultaneously within thermal limits. In this article, the authors investigate the limit ...
Keywords: Energy efficiency,Boosting,Transistors,Silicon,Semiconductor device manufacture,Logic gates,Parallel processing,Voltage control,energy-aware systems,low-power design

17
March 2013 IEEE Micro: Volume 33 Issue 2, March 2013
Publisher: IEEE Computer Society Press
Bibliometrics:
Citation Count: 7

Centip3De uses the synergy between 3D integration and near-threshold computing to create a reconfigurable system that provides both energy-efficient operation and techniques to address single-thread performance bottlenecks. The original Centip3De design is a seven-layer 3D stacked design with 128 cores and 256 Mbytes of DRAM. Silicon results show a two-layer, ...
Keywords: Random access memory,Three dimensional displays,Threshold voltage,Integrated circuit interconnections,Through-silicon vias,Power system management,Low power electronics,Centip3De,hardware,integrated circuits,types and design styles,advanced technologies,power management,low-power design

18
February 2013 HPCA '13: Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 11

In this paper, we explore the challenges in scaling on-chip networks towards kilo-core processors. Current low-radix topologies optimize for fast local communication, but do not scale well to kilo-core systems because of the large number of routers required. These increase both power and hop count. In contrast, symmetric high-radix topologies ...

19
December 2012 IEEE Transactions on Computers: Volume 61 Issue 12, December 2012
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 2

The rapid advancements in the computational capabilities of the graphics processing unit (GPU) as well as the deployment of general programming models for these devices have made the vision of a desktop supercomputer a reality. It is now possible to assemble a system that provides several TFLOPs of performance on ...
Keywords: Graphics processing unit,Benchmark testing,Computer architecture,Energy efficiency,Energy management,Low power electronics,Parallel processing,scientific computing,Low-power design,hardware,SIMD processors,processor architectures,parallel processors,Graphics Processing Unit (GPU),throughput computing

20 published by ACM
October 2012 CASES '12: Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Publisher: ACM
Bibliometrics:
Citation Count: 1
Downloads (6 Weeks): 0,   Downloads (12 Months): 2,   Downloads (Overall): 176

Full text available: PDFPDF
Just-in-time compilation with dynamic code optimization is often used to help improve the performance of applications that utilize high-level languages and virtual run-time environments, such as those found in smartphones. Just-in-time compilation introduces additional overhead into the instruction fetch stage of a processor that is particularly problematic for user applications-instruction ...
Keywords: architecture, instruction caching, self-modifying code, software-assisted coherence



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