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 Andrew Schwerin

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Bibliometrics: publication history
Average citations per article24.00
Citation Count144
Publication count6
Publication years2003-2007
Available for download6
Average downloads per article868.17
Downloads (cumulative)5,209
Downloads (12 Months)210
Downloads (6 Weeks)19
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6 results found Export Results: bibtexendnoteacmrefcsv

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1 published by ACM
May 2007 ACM Transactions on Computer Systems (TOCS): Volume 25 Issue 2, May 2007
Publisher: ACM
Bibliometrics:
Citation Count: 22
Downloads (6 Weeks): 10,   Downloads (12 Months): 52,   Downloads (Overall): 1,643

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Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, however, is an open challenge that conventional superscalar designs will not be able to meet. We present WaveScalar as a scalable alternative to conventional designs. WaveScalar is a ...
Keywords: dataflow computing, WaveScalar, multithreading

2 published by ACM
October 2006 ASPLOS XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Publisher: ACM
Bibliometrics:
Citation Count: 14
Downloads (6 Weeks): 2,   Downloads (12 Months): 26,   Downloads (Overall): 940

Full text available: PDFPDF
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effectively minimizes operand latency. After this schedule has been partitioned into large sections, the bottom-level algorithm must more carefully analyze program structure when producing the ...
Keywords: dataflow, instruction scheduling, tiled architectures
Also published in:
October 2006  ACM SIGOPS Operating Systems Review - Proceedings of the 2006 ASPLOS Conference: Volume 40 Issue 5, December 2006 November 2006  ACM SIGPLAN Notices - Proceedings of the 2006 ASPLOS Conference: Volume 41 Issue 11, November 2006 October 2006  ACM SIGARCH Computer Architecture News - Proceedings of the 2006 ASPLOS Conference: Volume 34 Issue 5, December 2006

3 published by ACM
September 2006 PACT '06: Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Publisher: ACM
Bibliometrics:
Citation Count: 3
Downloads (6 Weeks): 1,   Downloads (12 Months): 15,   Downloads (Overall): 406

Full text available: PDFPDF
In recent years, computer architects have proposed tiled architectures in response to several emerging problems in processor design, such as design complexity, wire delay, and fabrication reliability. One of these architectures, WaveScalar, uses a dynamic, tagged-token dataflow execution model to simplify the design of the processor tiles and their interconnection ...
Keywords: Wavescalar, compiler, tiled architecture, dataflow

4 published by ACM
July 2006 SPAA '06: Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Publisher: ACM
Bibliometrics:
Citation Count: 6
Downloads (6 Weeks): 3,   Downloads (12 Months): 8,   Downloads (Overall): 338

Full text available: PDFPDF
In response to current technology scaling trends, architects are developing a new style of processor, known as spatial computers. A spatial computer is composed of hundreds or even thousands of simple, replicated processing elements (or PEs), frequently organized into a grid. Several current spatial computers, such as TRIPS, RAW, SmartMemories, ...
Keywords: dataflow, instruction placement, spatial computing

5
May 2006 ISCA '06: Proceedings of the 33rd annual international symposium on Computer Architecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 12
Downloads (6 Weeks): 0,   Downloads (12 Months): 13,   Downloads (Overall): 553

Full text available: PDFPDF
Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and performance. The basic premise of these architectures is that larger, higher-performance implementations can be constructed by replicating the basic tile across the chip. This paper explores the area-performance trade-offs ...
Keywords: WaveScalar, Dataflow computing, ASIC, RTL
Also published in:
May 2006  ACM SIGARCH Computer Architecture News: Volume 34 Issue 2, May 2006

6
December 2003 MICRO 36: Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Publisher: IEEE Computer Society
Bibliometrics:
Citation Count: 77
Downloads (6 Weeks): 9,   Downloads (12 Months): 46,   Downloads (Overall): 1,116

Full text available: PDFPDF
Silicon technology will continue to provide an exponential increasein the availability of raw transistors. Effectively translatingthis resource into application performance, however,is an open challenge. Ever increasing wire-delay relativeto switching speed and the exponential cost of circuit complexitymake simply scaling up existing processor designs futile.In this paper, we present an alternative ...



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